• Verilog HDL Finite State Machine - Detecting decimal number

    From Tanishk Singh@21:1/5 to All on Sat Nov 6 21:56:17 2021
    Hi all,

    I am trying to build a sequence detector to detect a decimal number like 1092 when a stream of numbers from 0-9 is given as input. Do you think just changing the width of input i.e parallel inputs instead of series would result in pattern detection? I am
    lost in this, please help. If you have any resources around this do share them.

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  • From Richard Damon@21:1/5 to Tanishk Singh on Sun Nov 7 07:55:47 2021
    On 11/7/21 12:56 AM, Tanishk Singh wrote:
    Hi all,

    I am trying to build a sequence detector to detect a decimal number like 1092 when a stream of numbers from 0-9 is given as input. Do you think just changing the width of input i.e parallel inputs instead of series would result in pattern detection? I
    am lost in this, please help. If you have any resources around this do share them.


    You will need to define the problem a bit better, as currently it
    doesn't really make sense.

    Signals are just signals, so the concept of a 'decimal number' doesn't
    really have a meaning in that domain.

    You seem to be thinking in terms of a 'character string', so you are
    going to need to define how you are going to encode a character string
    into signals.

    An 8-bit parallel bus is one option, probably defined as 'ASCII' encoded.

    It could also be a 1 bit serial bus, maybe encoded in a standard UART
    data format, again 8 bit data, ASCII encoded.

    Without defining a representation and encoding you don;t have a problem
    to solve.

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