I am working on creating a FPGA implementation of a IBM 7000 series CPU. The bits are numbered with bit 0 as the most significant bit and bit n (n bits per word) as the least significant. Verilog seems to want the opposite order: bit 0 is the leastsignificant bit.
Does anyone know or has anyone tried numbering bits the other way around in Verilog?
I am working on creating a FPGA implementation of a IBM 7000 series CPU. The bits are numbered with bit 0 as the most significant bit and bit n (n bits per word) as the least significant. Verilog seems to want the opposite order: bit 0 is the leastsignificant bit.
Does anyone know or has anyone tried numbering bits the other way around in Verilog?
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