• IS there any open-sourse tool to convert SystemVerilog to Verilog?

    From Nasrin Eshraghi@21:1/5 to All on Fri Oct 12 07:50:50 2018
    Hello

    I have codes wanting to have output as a Verilog code, Is there any tool which can do it?


    Many thanks

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  • From dsc@21:1/5 to All on Sat Oct 13 00:05:01 2018
    What do you mean? System Verilog is completely based on Verilog + extra. What kind of output do you need? There won’t be a tool such as that. (Not a perfect example but would be like having a tool to turn C++ into C.)

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