• verilog

    From Niharika Behera@21:1/5 to All on Fri Sep 3 23:06:11 2021
    can u tell me verilog syntax of 4bit signed multiplier

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  • From project Amar@21:1/5 to niharika...@gmail.com on Sat Sep 4 12:04:53 2021
    On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
    can u tell me verilog syntax of 4bit signed multiplier

    I can do this for you (with best way) , price : 5$ , im verilog freelancer

    Do you want to it?

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  • From Verilog Freelancer@21:1/5 to niharika...@gmail.com on Sat Sep 4 12:44:34 2021
    On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
    can u tell me verilog syntax of 4bit signed multiplier
    can do this for you (with best way) , price : 5$ , im verilog freelancer

    Do you want to it?

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  • From Verilog Freelancer@21:1/5 to niharika...@gmail.com on Sat Sep 4 12:45:32 2021
    On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
    can u tell me verilog syntax of 4bit signed multiplier
    .
    .
    i can do this for you (with best way) , price : 5$ , im verilog freelancer

    Do you want to it?

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  • From Richard Damon@21:1/5 to Niharika Behera on Sat Sep 4 16:34:00 2021
    On 9/4/21 2:06 AM, Niharika Behera wrote:
    can u tell me verilog syntax of 4bit signed multiplier


    You mean like:

    signed wire [3:0] a;
    signed wire [3:0] b;
    signed wire [3:0] c;

    assign c = a * b;

    (pulled off the top of my head and may have some details wrong, you get
    exactly what you paid for it).

    Be prepared for a lousy implementation.

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  • From Niharika Behera@21:1/5 to Richard Damon on Sat Sep 4 22:25:16 2021
    On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote:
    On 9/4/21 2:06 AM, Niharika Behera wrote:
    can u tell me verilog syntax of 4bit signed multiplier

    You mean like:

    signed wire [3:0] a;
    signed wire [3:0] b;
    signed wire [3:0] c;

    assign c = a * b;

    (pulled off the top of my head and may have some details wrong, you get exactly what you paid for it).

    Be prepared for a lousy implementation.
    this format is wrong

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  • From Niharika Behera@21:1/5 to Niharika Behera on Sat Sep 4 22:41:17 2021
    On Saturday, September 4, 2021 at 11:36:13 AM UTC+5:30, Niharika Behera wrote:
    can u tell me verilog syntax of 4bit signed multiplier...
    this is my code in vivardo....
    input [4:1] a,b;
    output [8:1] y;
    wire signed [7:1]a1;
    wire signed[7:1]b1;
    wire [16:1]mul;
    assign a1[4:1]=~a|1;
    assign b1[4:1]=~b|1;
    assign a1[7:5]=4'b1111;
    assign b1[7:5]=4'b1111;
    assign mul=a1*b1;
    assign y=mul[8:1];
    endmodule

    any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
    but i need -3 answer.....i am dought in last 4 steps...help me...

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  • From Niharika Behera@21:1/5 to Richard Damon on Mon Sep 6 00:19:10 2021
    On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote:
    On 9/4/21 2:06 AM, Niharika Behera wrote:
    can u tell me verilog syntax of 4bit signed multiplier

    You mean like:

    signed wire [3:0] a;
    signed wire [3:0] b;
    signed wire [3:0] c;

    assign c = a * b;

    (pulled off the top of my head and may have some details wrong, you get exactly what you paid for it).

    Be prepared for a lousy implementation.
    On Saturday, September 4, 2021 at 11:36:13 AM UTC+5:30, Niharika Behera wrote:
    can u tell me verilog syntax of 4bit signed multiplier...
    this is my code in vivardo....
    input [4:1] a,b;
    output [8:1] y;
    wire signed [7:1]a1;
    wire signed[7:1]b1;
    wire [16:1]mul;
    assign a1[4:1]=~a|1;
    assign b1[4:1]=~b|1;
    assign a1[7:5]=4'b1111;
    assign b1[7:5]=4'b1111;
    assign mul=a1*b1;
    assign y=mul[8:1];
    endmodule

    any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
    but i need -3 answer.....i am dought in last 4 steps...help me...

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  • From Niharika Behera@21:1/5 to verilog.f...@gmail.com on Mon Sep 6 00:19:31 2021
    On Sunday, September 5, 2021 at 1:15:34 AM UTC+5:30, verilog.f...@gmail.com wrote:
    On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
    can u tell me verilog syntax of 4bit signed multiplier
    .
    .
    i can do this for you (with best way) , price : 5$ , im verilog freelancer

    Do you want to it?

    this is my code in vivado....
    input [4:1] a,b;
    output [8:1] y;
    wire signed [7:1]a1;
    wire signed[7:1]b1;
    wire [16:1]mul;
    assign a1[4:1]=~a|1;
    assign b1[4:1]=~b|1;
    assign a1[7:5]=4'b1111;
    assign b1[7:5]=4'b1111;
    assign mul=a1*b1;
    assign y=mul[8:1];
    endmodule

    any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
    but i need -3 answer.....i am dought in last 4 steps...help me...

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  • From Verilog Freelancer@21:1/5 to All on Mon Sep 6 13:46:40 2021
    any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
    but i need -3 answer.....i am dought in last 4 steps...help me...


    Your code is incorrect , try other ways

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  • From project Amar@21:1/5 to All on Mon Sep 6 13:40:03 2021
    your code is the mistake. try any way

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  • From TJ Edmister@21:1/5 to niharikabehera65@gmail.com on Thu Sep 16 11:08:40 2021
    On Sun, 05 Sep 2021 01:25:16 -0400, Niharika Behera <niharikabehera65@gmail.com> wrote:

    On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote:
    On 9/4/21 2:06 AM, Niharika Behera wrote:
    can u tell me verilog syntax of 4bit signed multiplier

    You mean like:

    signed wire [3:0] a;
    signed wire [3:0] b;
    signed wire [3:0] c;

    assign c = a * b;

    (pulled off the top of my head and may have some details wrong, you get
    exactly what you paid for it).

    Be prepared for a lousy implementation.
    this format is wrong

    When the result of a multiply has only the same number of bits as the
    input values, there is effectively no difference between a signed and an unsigned multiply operation. Assuming you want more than 4 bits in the
    result, is there any reason why Richard Damon's code would not work with
    'c' having a larger size? I have not tried it myself.

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  • From Richard Damon@21:1/5 to TJ Edmister on Thu Sep 16 22:24:37 2021
    On 9/16/21 11:08 AM, TJ Edmister wrote:
    On Sun, 05 Sep 2021 01:25:16 -0400, Niharika Behera <niharikabehera65@gmail.com> wrote:

    On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote: >>> On 9/4/21 2:06 AM, Niharika Behera wrote:
    can u tell me verilog syntax of 4bit signed multiplier

    You mean like:

    signed wire [3:0] a;
    signed wire [3:0] b;
    signed wire [3:0] c;

    assign c = a * b;

    (pulled off the top of my head and may have some details wrong, you get
    exactly what you paid for it).

    Be prepared for a lousy implementation.
    this format is wrong

    When the result of a multiply has only the same number of bits as the
    input values, there is effectively no difference between a signed and an unsigned multiply operation. Assuming you want more than 4 bits in the result, is there any reason why Richard Damon's code would not work with
    'c' having a larger size? I have not tried it myself.

    It might be it needs to be wire signed instead of signed wire.

    I don't do enough with signed signals to remember the syntax, so I look
    it up when needed (or get the error and try the other order).

    That is way I disclaimed about some details may be wrong.

    If it was homework, and they couldn't fix that, they deserve the
    problems. If it didn't give them enough to get started, they aren't
    really trying to learn.

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