Calculating the average in Verilog
From
smriti thakur@21:1/5 to
All on Tue May 18 22:37:47 2021
hey follow this hope this can help
module Mean(in_n0,in_n1,in_n2,in_n3,out_mean);
input [3:0] in_n0,in_n1,in_n2,in_n3;
output reg [4:0] out_mean;
wire [5:0] w0,w1,w2,w3,sum;
assign w0={{2{in_n0[3]}},in_n0};
assign w1={{2{in_n1[3]}},in_n1};
assign w2={{2{in_n2[3]}},in_n2};
assign w3={{2{in_n3[3]}},in_n3};
assign sum=w0+w1+w2+w3;
always@*begin
if(sum[5]==1)
out_mean={sum[5],sum[5:2]}+{4'b0000,(sum[1]|sum[0])};
else
out_mean={sum[5],sum[5:2]};
end
endmodule
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