• How powerful is Verilog at using parameters to specify designs?

    From Kevin Simonson@21:1/5 to All on Mon Sep 21 15:24:42 2020
    I have a design in mind that would fit in this skeleton:
    [code]
    module xyz ( result, leftOp, rightOp);
    parameter integer nmBits = 1;
    localparam integer highBit = nmBits - 1;
    output result;
    input [ highBit:0] leftOp;
    input [ highBit:0] rightOp;

    // ...

    endmodule
    [/code]
    The way (xyz) is designed, this module would work differently for different values of (nmBits), but in a way that can be precisely defined. In fact, I'm seriously thinking of writing a Java program that takes (nmBits) as an input and produces a
    parameterless verion of (xyz) for that version of (nmBits). So I'm wondering, is it a true statement that, if one can write such a Java program to produce the equivalent (parameterless) Verilog code for any given set of parameters, one can also write
    Verilog code with parameters to do the same thing?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From TJ Edmister@21:1/5 to All on Sat Oct 3 07:03:51 2020
    I used parameters defined at the beginning of a module to specify the 'bit width' of the module, including both internal registers and an external
    bus. Something like this:

    module example (clk, reset, ddatabus);
    parameter regmsb = 17; // highest bit number - determines bus width
    input clk;
    input reset;
    input [regmsb:0] ddatabus;
    reg [regmsb:0] internalreg;

    [...]

    I'm not sure if there is a way to define the parameters outside the
    module, such that you could include multiple, different variations of a
    module in one project.

    On Mon, 21 Sep 2020 18:24:42 -0400, Kevin Simonson <kvnsmnsn@hotmail.com> wrote:

    I have a design in mind that would fit in this skeleton:
    [code]
    module xyz ( result, leftOp, rightOp);
    parameter integer nmBits = 1;
    localparam integer highBit = nmBits - 1;
    output result;
    input [ highBit:0] leftOp;
    input [ highBit:0] rightOp;

    // ...

    endmodule
    [/code]
    The way (xyz) is designed, this module would work differently for
    different values of (nmBits), but in a way that can be precisely
    defined. In fact, I'm seriously thinking of writing a Java program that
    takes (nmBits) as an input and produces a parameterless verion of (xyz)
    for that version of (nmBits). So I'm wondering, is it a true statement
    that, if one can write such a Java program to produce the equivalent (parameterless) Verilog code for any given set of parameters, one can
    also write Verilog code with parameters to do the same thing?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Remigiusz Kaletka@21:1/5 to All on Wed Oct 14 04:08:40 2020
    sobota, 3 października 2020 o 13:03:44 UTC+2 TJ Edmister napisał(a):
    I used parameters defined at the beginning of a module to specify the 'bit width' of the module, including both internal registers and an external
    bus. Something like this:

    module example (clk, reset, ddatabus);
    parameter regmsb = 17; // highest bit number -
    determines bus width
    input clk;
    input reset;
    input [regmsb:0] ddatabus;
    reg [regmsb:0] internalreg;

    [...]

    I'm not sure if there is a way to define the parameters outside the
    module, such that you could include multiple, different variations of a module in one project.

    On Mon, 21 Sep 2020 18:24:42 -0400, Kevin Simonson <kvns...@hotmail.com> wrote:
    I have a design in mind that would fit in this skeleton:
    [code]
    module xyz ( result, leftOp, rightOp);
    parameter integer nmBits = 1;
    localparam integer highBit = nmBits - 1;
    output result;
    input [ highBit:0] leftOp;
    input [ highBit:0] rightOp;

    // ...

    endmodule
    [/code]
    The way (xyz) is designed, this module would work differently for different values of (nmBits), but in a way that can be precisely
    defined. In fact, I'm seriously thinking of writing a Java program that takes (nmBits) as an input and produces a parameterless verion of (xyz) for that version of (nmBits). So I'm wondering, is it a true statement that, if one can write such a Java program to produce the equivalent (parameterless) Verilog code for any given set of parameters, one can
    also write Verilog code with parameters to do the same thing?

    There is no problem with that, just specify design inside generate/endgenerate block with if covering every case. Then instantiate mutliple module with different parameters in parent module.
    You go like this:

    generate
    if (highbit == 1) begin
    <code>
    end
    else if (highbit == 2) begin
    <code>
    end
    else begin
    <specify default behaviour>
    end
    endgenerate

    If it's one specific operation during something longer, you can also use parameters in regular always block, both ways it is begin "translated" to different modules during synthesis.

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    * Origin: fsxNet Usenet Gateway (21:1/5)