• initialize output nodes

    From paslarerfan1@gmail.com@21:1/5 to Alex on Fri Jun 12 10:30:49 2020
    On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
    Hi everybody,
    Does anyone could help me ?
    I'm currently trying to simulate a JK flip-flop Verilog-netlisted from
    a schematic. And as Q is equal to x at the beginning, it always stays
    at x...
    So i need to initialize Q, but as it is an output it doesn 't work,
    even if i put it as an inout.
    Could you give me some tips ?
    Thanks by advance,
    Alex

    I'm having the same problem in simulation if anyone know how to initialize the output Q at first time please tell us.

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  • From Rick C@21:1/5 to paslar...@gmail.com on Fri Jun 12 14:48:44 2020
    On Friday, June 12, 2020 at 1:30:52 PM UTC-4, paslar...@gmail.com wrote:
    On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
    Hi everybody,
    Does anyone could help me ?
    I'm currently trying to simulate a JK flip-flop Verilog-netlisted from
    a schematic. And as Q is equal to x at the beginning, it always stays
    at x...
    So i need to initialize Q, but as it is an output it doesn 't work,
    even if i put it as an inout.
    Could you give me some tips ?
    Thanks by advance,
    Alex

    I'm having the same problem in simulation if anyone know how to initialize the output Q at first time please tell us.

    Isn't that what initial blocks are for?

    --

    Rick C.

    - Get 1,000 miles of free Supercharging
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  • From TJ Edmister@21:1/5 to paslarerfan1@gmail.com on Sat Jun 13 09:40:14 2020
    On Fri, 12 Jun 2020 13:30:49 -0400, <paslarerfan1@gmail.com> wrote:

    On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
    Hi everybody,
    Does anyone could help me ?
    I'm currently trying to simulate a JK flip-flop Verilog-netlisted from
    a schematic. And as Q is equal to x at the beginning, it always stays
    at x...
    So i need to initialize Q, but as it is an output it doesn 't work,
    even if i put it as an inout.
    Could you give me some tips ?
    Thanks by advance,
    Alex

    I'm having the same problem in simulation if anyone know how to
    initialize the output Q at first time please tell us.

    Can you not use something like this?

    initial q = 0;

    Using Icarus verilog, I've also been a bit frustrated by getting x's everywhere. It seems that it will even give you a result of 'x' in cases
    where I would expect a real answer, like 'x' AND 0, or 'x' multiplied by
    0. It would be nice if the simulator could be directed to automatically
    make all registers zero, or fill them with random data, instead of me
    having to manually specify it. However I could not find such an option in
    the documentation.

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  • From Rick C@21:1/5 to TJ Edmister on Sat Jun 13 17:18:43 2020
    On Saturday, June 13, 2020 at 9:40:04 AM UTC-4, TJ Edmister wrote:
    On Fri, 12 Jun 2020 13:30:49 -0400, <paslarerfan1@gmail.com> wrote:

    On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
    Hi everybody,
    Does anyone could help me ?
    I'm currently trying to simulate a JK flip-flop Verilog-netlisted from
    a schematic. And as Q is equal to x at the beginning, it always stays
    at x...
    So i need to initialize Q, but as it is an output it doesn 't work,
    even if i put it as an inout.
    Could you give me some tips ?
    Thanks by advance,
    Alex

    I'm having the same problem in simulation if anyone know how to initialize the output Q at first time please tell us.

    Can you not use something like this?

    initial q = 0;

    Using Icarus verilog, I've also been a bit frustrated by getting x's everywhere. It seems that it will even give you a result of 'x' in cases where I would expect a real answer, like 'x' AND 0, or 'x' multiplied by
    0. It would be nice if the simulator could be directed to automatically make all registers zero, or fill them with random data, instead of me having to manually specify it. However I could not find such an option in the documentation.

    Initialization is not always a good idea unless your circuit will also provide initialization. But then your simulator should simulate logic functions properly. In VHDL anything anded with '0' is '0'. Are you sure that's not the same in Verilog? It
    would be very hard to get rid of the various non-logic states otherwise.

    --

    Rick C.

    - Get 1,000 miles of free Supercharging
    - Tesla referral code - https://ts.la/richard11209

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