• how to simulate verilog with rom in modelsim?

    From getdip43@gmail.com@21:1/5 to All on Tue Jun 9 23:59:28 2020
    Thanks a lot, the hex file was included
    in the work and I included the altera_sym_ver library as well but the output was always zero, finally it worked by changing the dictory to full path in my rom.v file.

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