In the testbench below (tested using Modelsim FPGA starter edition), the contents of interfaces "c" do not update when interface "b" changes state. Is this behaviour to be expected? Thanks.


interface uut_interface #( parameter N = 0) ();
logic [N-1:0] [7:0] x;
endinterface

module tb;
uut_interface #(.N(2)) b ();

genvar n;
generate
for (n = 0; n < 2; n++)
begin
uut_interface #(.N(1)) c ();

always_comb
begin
c.x = b.x [n];
end
// assign c.x = b.x [n];

initial
begin
b.x [n] = 0;
#1
b.x[n] <= 1;
#1
b.x[n] <= 2;
#1
b.x[n] <= 3;
$stop;
end
end
endgenerate
endmodule

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