Hi all,couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a
https://i.postimg.cc/HLDFnmFZ/bidir.jpg
https://i.postimg.cc/XvfMVrs7/bidir-2.jpg
Any help or suggestion is appreciated.Thanks in advance.
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a
ASIC devices that aren't the same way.https://i.postimg.cc/HLDFnmFZ/bidir.jpg
https://i.postimg.cc/XvfMVrs7/bidir-2.jpg
Any help or suggestion is appreciated.Thanks in advance.
I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.
However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find many
Is this for an external bus?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a
ASIC devices that aren't the same way.
https://i.postimg.cc/HLDFnmFZ/bidir.jpg
https://i.postimg.cc/XvfMVrs7/bidir-2.jpg
Any help or suggestion is appreciated.Thanks in advance.
I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.
However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find many
the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.
Is this for an external bus?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in
On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a
many ASIC devices that aren't the same way.https://i.postimg.cc/HLDFnmFZ/bidir.jpg
https://i.postimg.cc/XvfMVrs7/bidir-2.jpg
Any help or suggestion is appreciated.Thanks in advance.
I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.
However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find
the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.Is this for an external bus?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in
On Tuesday, April 28, 2020 at 3:40:40 PM UTC-4, bri...@gmail.com wrote:a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:
On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are
many ASIC devices that aren't the same way.https://i.postimg.cc/HLDFnmFZ/bidir.jpg
https://i.postimg.cc/XvfMVrs7/bidir-2.jpg
Any help or suggestion is appreciated.Thanks in advance.
I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.
However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find
the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.Is this for an external bus?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in
A crash in what system, the tools or your hardware?
Why don't you paste your '245 model code? It can't be very much code. It should be less than half a dozen lines. In VHDL this would be one line of code depending on the length of your signal names.
IO_bus <= (others => 'Z') when Tristate_En = '0' else Internal_bus;
I imagine the Verilog is very similar.
--
Rick C.
+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
On Tuesday, 28 April 2020 22:31:55 UTC+2, Rick C wrote:are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:
On Tuesday, April 28, 2020 at 3:40:40 PM UTC-4, bri...@gmail.com wrote:
On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There
many ASIC devices that aren't the same way.https://i.postimg.cc/HLDFnmFZ/bidir.jpg
https://i.postimg.cc/XvfMVrs7/bidir-2.jpg
Any help or suggestion is appreciated.Thanks in advance.
I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.
However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find
in the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.Is this for an external bus?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash
A crash in what system, the tools or your hardware?
Why don't you paste your '245 model code? It can't be very much code. It should be less than half a dozen lines. In VHDL this would be one line of code depending on the length of your signal names.
IO_bus <= (others => 'Z') when Tristate_En = '0' else Internal_bus;
I imagine the Verilog is very similar.
--
Rick C.
+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
Well, as i said I'm not yer familiar with writing code so I ported to Quartus the logic diagram of the 74245 (from whatever datasheet) and made a BDF file (and a BSF too for the symbol) :
http://www.mediafire.com/file/5evap6f2lmq7mq5/IC74245.bdf/file
I also found a couple of Verilog implementation of the 74245 :
Library ieee;
Use ieee.std_logic_1164.all;
Entity VHDL_74245 is
Port(G_L,DIR: in std_logic;
A,B: inout std_logic_vector(7 downto 0);
Y: out std_logic_vector(7 downto 0));
End VHDL_74245;
Architecture behav of VHDL_74245 is
Begin
Process (G_L, DIR, A,B)
Begin
If(G_L='0' and DIR='1') then
B<=A;
Elsif (G_L='0' and DIR='0') then
A<=B;
End if;
End process;
End behav;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CPLD_74LS245 is
Port ( nE : in STD_LOGIC;
dir : in STD_LOGIC;
B : inout STD_LOGIC_VECTOR (7 downto 0);
A : inout STD_LOGIC_VECTOR (7 downto 0));
end CPLD_74LS245;
architecture Behavioral of CPLD_74LS245 is
begin
-- Wenn nE = 1 oder dir = '1' dann HighZ
-- Sonst B
A <= (7 downto 0 => 'Z') when nE = '1' OR dir = '1' else B;
-- Wenn nE = 1 oder dir = '1' dann HighZ
-- Sonst A
B <= (7 downto 0 => 'Z') when nE = '1' OR dir = '0' else A;
end Behavioral;
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Zstate when you aren't driving data.
Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
Z state when you aren't driving data.The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-
Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :
http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file
Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)
http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file
I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.
Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.
--
Rick C.
+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
Z state when you aren't driving data.The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-
Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :
http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file
Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)
http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file
I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
state when you aren't driving data.The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z
Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :
http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file
Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)
http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
high-Z state when you aren't driving data.The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a
whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :
http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file
Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)
http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file
I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.
Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.
--
Rick C.
+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design
Hi all,couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a
On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
high-Z state when you aren't driving data.The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a
design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :
http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file
Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)
http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file
I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.
Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.
--
Rick C.
+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD
I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.
On Wednesday, April 29, 2020 at 6:44:37 AM UTC-4, bri...@gmail.com wrote:modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
high-Z state when you aren't driving data.The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a
design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :
http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file
Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)
http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file
I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.
Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.
--
Rick C.
+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD
A and the other B as in your schematic.I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.
Ok, that is more clear. I will say the EPM7128 is very much overkill for this design, but that's ok. Better too large than too small. So the code I gave you should do the job here is an example that does the full in and out of the '245. One I/O is
signal DA, DB : std_logic_vector (7 downto 0);8 lines back to themselves. Or maybe you are trying to replace one of the higher complexity bus interface devices that aren't made anymore?
signal s402_2H, s401_fi, other_ck, s601 : std_logic;
signal RD_n, s603, s602, wait_n, FF1, FF2 : std_logic;
DA <= 'Z' when (s602 or RD_n = '1') else DB;
DB <= 'Z' when (s602 or not RD_n = '1') else DA;
wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;
process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck))
FF1 <= s401_fi;
end if;
if (falling_edge(other_ck))
FF2 <= FF1;
end if;
end process;
This is the logic as shown on the page. It still needs the entity boilerplate to define the I/Os for the device which are the signals on the 28 pin connector.
Can you tell me what the design does? The '245 device seems to simple connect pins on the 28 pin socket back to itself, either in one direction or the other. What plugs into the socket??? It would appear to be an MCU which makes little sense to tie
There are a couple of parts of the schematic that are troubling. One is the use of the PREset pin on the FF. PREset and CLR are asynchronous logic (combinational) and have very particular timing constraints which will be very different inside theCPLD and a TTL device. Without a thorough understanding of the design it is hard to know if this will work well. It is better to use the synchronous logic with separate combinational logic. That can only be done with detailed info on the intended
The same thing applies to the use of two inverters to create the enable on the '245 device. This is a logic noop which will only create an ill defined delay. This is hard to do in a CPLD since the tools will optimize it out. It has the same timingconcerns as the PREset on the FF.
The more info you can provide, the more help you can get.
--
Rick C.
++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209
On Wednesday, 29 April 2020 21:48:55 UTC+2, Rick C wrote:something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).
On Wednesday, April 29, 2020 at 6:44:37 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.
Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.
-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);
io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end process io_buf;
io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.
A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want
io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;
B = Y;
end procedure io_buf;
a high-Z state when you aren't driving data.The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to
design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.Y <= 'Z' when (OE = '0') else A;
You can add this if it is more clear
B <= Y;
Sorry if this doesn't help you. I was bored and it was useful for me to review.
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :
http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file
Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)
http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file
I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.
Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.
--
Rick C.
+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD
is A and the other B as in your schematic.I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.
Ok, that is more clear. I will say the EPM7128 is very much overkill for this design, but that's ok. Better too large than too small. So the code I gave you should do the job here is an example that does the full in and out of the '245. One I/O
tie 8 lines back to themselves. Or maybe you are trying to replace one of the higher complexity bus interface devices that aren't made anymore?signal DA, DB : std_logic_vector (7 downto 0);
signal s402_2H, s401_fi, other_ck, s601 : std_logic;
signal RD_n, s603, s602, wait_n, FF1, FF2 : std_logic;
DA <= 'Z' when (s602 or RD_n = '1') else DB;
DB <= 'Z' when (s602 or not RD_n = '1') else DA;
wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;
process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck))
FF1 <= s401_fi;
end if;
if (falling_edge(other_ck))
FF2 <= FF1;
end if;
end process;
This is the logic as shown on the page. It still needs the entity boilerplate to define the I/Os for the device which are the signals on the 28 pin connector.
Can you tell me what the design does? The '245 device seems to simple connect pins on the 28 pin socket back to itself, either in one direction or the other. What plugs into the socket??? It would appear to be an MCU which makes little sense to
CPLD and a TTL device. Without a thorough understanding of the design it is hard to know if this will work well. It is better to use the synchronous logic with separate combinational logic. That can only be done with detailed info on the intendedThere are a couple of parts of the schematic that are troubling. One is the use of the PREset pin on the FF. PREset and CLR are asynchronous logic (combinational) and have very particular timing constraints which will be very different inside the
concerns as the PREset on the FF.The same thing applies to the use of two inverters to create the enable on the '245 device. This is a logic noop which will only create an ill defined delay. This is hard to do in a CPLD since the tools will optimize it out. It has the same timing
a able to keep the same dimensions of original part by using surface mounted TTLs.But I have other with very big circuit, that's why I want to practice with CPLD.As said, for now I can only translate my TTL schematics into Quartus block diagram, I knowThe more info you can provide, the more help you can get.
--
Rick C.
++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209
You got closer :) The design is a replacement of a custom IC used on some arcade boards.I've succesfully done reverse-engineering of this (and many other) custom ICs but I used simple TTL gates to achieve the result.This one has few logics hence I was
As for you code, I would gladly try it but, forgive my ignorancy, I don't know how to define the I/0 inside VHDL and Verilog.
With the entity declaration added the VHDL code becomeswill simulate the design.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0);
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic;
s603, s602, wait_n : out std_logic
);
end Thing ;
architecture V1 of Thing is
signal FF1, FF2, OE : std_logic;
begin
DA <= 'Z' when ((OE and not RD_n) = '0') else DB;
DB <= 'Z' when ((OE and RD_n) = '0') else DA;
wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;
OE <= FF1 and FF2 and not s601;
process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi;
end if;
if (falling_edge(other_ck)) then
FF2 <= FF1;
end if;
end process;
end V1;
I don't have a track record of getting things right the first time. I don't see any issues with this code but that may not mean much, lol.
You can simulate the design on the computer if you know what the waveforms at IC1 should be. I assume you have a working device you can scope? If you can capture a few waveforms showing the typical cycles of operation I can generate a test bench that
The signal to the enable pin on the '245 chip (G) is driven through two inverters most likely for the delay. I assume this is to allow what ever is driving the bus from the other side to turn off from the 602 signal so they aren't fighting. I createdseparate logic to enable the buffer from the 602 signal, but it is hard to add delays. It can be done by adding an attribute to an intermediate wire, but even then delays in CPLDs and FPGAs are partly due to routing. CPLDs have fewer routing options so
--
Rick C.
--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209
Hi all,couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a
https://i.postimg.cc/HLDFnmFZ/bidir.jpg
https://i.postimg.cc/XvfMVrs7/bidir-2.jpg
Any help or suggestion is appreciated.Thanks in advance.
Thanks for your words, I only hope to not end up washing dishes ahahaha Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :
Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal
I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).
As for FPGA practicing I spotted this cheap dev board to play with :
http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board
On Thursday, April 30, 2020 at 5:36:44 AM UTC-4, Caius wrote:
Thanks for your words, I only hope to not end up washing dishes ahahaha Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :
Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal
I did give a disclaimer about my getting things right the first go. I found four errors, names can't begin with a numeric digit, I used -> instead of => in the aggregate (others =>), read an output and forgot required parens in a couple of places.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;
architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;
begin
DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;
wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= (not s601) and FF1 and FF2 ;
s602 <= s602_int ;
process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;
if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;
This one at least has no syntax errors.
I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).
All of the control signals would be good. One bit of each bus might help understand when it goes tristate. Are there memory cycles going on? I/O cycles? Where did the names 602, 603, etc. come from? Yours or on the unit?
your design.As for FPGA practicing I spotted this cheap dev board to play with :
http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board
Might be good. Needs a programming cable. I see one on eBay under $20 with a cable. https://www.ebay.com/itm/222882868419 Very slow shipping.
I would suggest you look at the TinyFPGA boards. The BX includes the programmer on the module. It's $40, but you can mount the module directly on your board. https://tinyfpga.com/ There's a number of Lattice based dev boards about.
There's also an interesting board with a Gowin part (new Chinese company). It's got a lot on it. Just $11 including shipping. Interfaces to a $17, 5 inch color LCD display. Not bad if you can use that. Otherwise it is small enough to be used in
https://www.ebay.com/i/184024583893?chn=ps&var=691716640114#
I haven't used Gowin's tools yet. I expect they work adequately.
--
Rick C.
-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209
On Thursday, 30 April 2020 21:56:22 UTC+2, Rick C wrote:
On Thursday, April 30, 2020 at 5:36:44 AM UTC-4, Caius wrote:
Thanks for your words, I only hope to not end up washing dishes ahahaha Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :
Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal
I did give a disclaimer about my getting things right the first go. I found four errors, names can't begin with a numeric digit, I used -> instead of => in the aggregate (others =>), read an output and forgot required parens in a couple of places.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;
architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;
begin
DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;
wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= (not s601) and FF1 and FF2 ;
s602 <= s602_int ;
process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;
if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;
This one at least has no syntax errors.
I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).
All of the control signals would be good. One bit of each bus might help understand when it goes tristate. Are there memory cycles going on? I/O cycles? Where did the names 602, 603, etc. come from? Yours or on the unit?
your design.As for FPGA practicing I spotted this cheap dev board to play with :
http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board
Might be good. Needs a programming cable. I see one on eBay under $20 with a cable. https://www.ebay.com/itm/222882868419 Very slow shipping.
I would suggest you look at the TinyFPGA boards. The BX includes the programmer on the module. It's $40, but you can mount the module directly on your board. https://tinyfpga.com/ There's a number of Lattice based dev boards about.
There's also an interesting board with a Gowin part (new Chinese company). It's got a lot on it. Just $11 including shipping. Interfaces to a $17, 5 inch color LCD display. Not bad if you can use that. Otherwise it is small enough to be used in
https://www.ebay.com/i/184024583893?chn=ps&var=691716640114#
I haven't used Gowin's tools yet. I expect they work adequately.
--
Rick C.
-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209
I tried the code, the hosting hardware (the arcade board) is watchdogging and keeps resetting in an endless loop.Just to be sure we used same pin labeling, is your DB0-DB7 the DB0-DB7 of my schematics (and your DA0-DA7 my D0-D7)?
Anywyay, thanks for wasting your time with this thing (and indeed you called it 'Thing'...)
Thanks also for the links of the FPGA dev boards, I gonna to purchase some to play with :)
P.S.
I think the labeling of my schematics come from the schematics of the arcade board but I can't exactly remember now.I'll check and let you know.
On Thursday, April 30, 2020 at 6:24:14 PM UTC-4, Caius wrote:
On Thursday, 30 April 2020 21:56:22 UTC+2, Rick C wrote:
On Thursday, April 30, 2020 at 5:36:44 AM UTC-4, Caius wrote:
Thanks for your words, I only hope to not end up washing dishes ahahaha Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :
Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal
I did give a disclaimer about my getting things right the first go. I found four errors, names can't begin with a numeric digit, I used -> instead of => in the aggregate (others =>), read an output and forgot required parens in a couple of places.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;
architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;
begin
DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;
wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= (not s601) and FF1 and FF2 ;
s602 <= s602_int ;
process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;
if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;
This one at least has no syntax errors.
I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).
All of the control signals would be good. One bit of each bus might help understand when it goes tristate. Are there memory cycles going on? I/O cycles? Where did the names 602, 603, etc. come from? Yours or on the unit?
in your design.As for FPGA practicing I spotted this cheap dev board to play with :
http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board
Might be good. Needs a programming cable. I see one on eBay under $20 with a cable. https://www.ebay.com/itm/222882868419 Very slow shipping.
I would suggest you look at the TinyFPGA boards. The BX includes the programmer on the module. It's $40, but you can mount the module directly on your board. https://tinyfpga.com/ There's a number of Lattice based dev boards about.
There's also an interesting board with a Gowin part (new Chinese company). It's got a lot on it. Just $11 including shipping. Interfaces to a $17, 5 inch color LCD display. Not bad if you can use that. Otherwise it is small enough to be used
https://www.ebay.com/i/184024583893?chn=ps&var=691716640114#
I haven't used Gowin's tools yet. I expect they work adequately.
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Rick C.
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I tried the code, the hosting hardware (the arcade board) is watchdogging and keeps resetting in an endless loop.Just to be sure we used same pin labeling, is your DB0-DB7 the DB0-DB7 of my schematics (and your DA0-DA7 my D0-D7)?
Good thing you asked. DA and DB in my code correspond to the A and B buses on the '245 chip. So DA in the code is DB on your schematic and DB in the code is D on your schematic.
Anywyay, thanks for wasting your time with this thing (and indeed you called it 'Thing'...)
Thanks also for the links of the FPGA dev boards, I gonna to purchase some to play with :)
P.S.
I think the labeling of my schematics come from the schematics of the arcade board but I can't exactly remember now.I'll check and let you know.
I'm just looking for meaning in any of the signal names. Do you have a schematic of the arcade board??? That would help tremendously... at least if the chips aren't all Thing_1 and Thing_2.
You know I'm going to expect you to name your first born after me, right?
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Rick C.
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I reviewed the pin assignement and tried again your code, it works fine in a board but not in another.
The one in which it works is Green Beret, full schematics here (the IC is labeled '501' at location '3C')
http://pdf.textfiles.com/manuals/ARCADE/A-J/Green%20Beret%20[Schematics]%20[English].pdf
The board that doesn't work with your code (it's watchdogging) is Time Pilot, schematics here (the IC is the one labeled 'C3' @IC2 on top left of PDF)
http://pdf.textfiles.com/manuals/ARCADE/S-Z/Time%20Pilot%20(CPU%20600dpi)%20[Schematics]%20[English].pdf
Thanks again for spending your time with this.
I only see one part that might be the "patch board" for the custom chip, it's labeled "501" and "5C", not "3C".
Now I'm confused about the buses. In the Green Beret schematic bus DB is on pins numbered 1 to 8 and bus D is on pins numbered 20 to 27. That is opposite your schematic for the internals. I suppose that was an error made by the original designer ofthe "patch" board who had it working, so all is really ok. The Time Pilot board has the buses labeled the other way I just realized, so that's the source of the problem.
Pins 15 and 16 are not shown for the Green Beret. Your drawing shows them not connected. That seems ok.
Green Beret shows pin 18 going to the 200 pin mystery chip as an input. Any info on that guy? The signal is labeled "BUS".giant mystery chip.
In your schematic pin 17 is "603". The Green Beret has nothing connected if I understand the notation. Please confirm. On Time Pilot this is F2 and pin 12 connects to F3. I can't find the source of either. On Green Beret pin 12 is CS501 from the
Pin 9 goes to the 2H signal on the Green Beret again from the giant mystery chip. On Time Pilot it is G2 from IC3, a small mystery chip. Also pin 10, G1 on Time Pilot is X15 on Green Beret, the CPU clock inverted. Pin 11 is the chip clock ~6 MHz onTime Pilot, from the giant mystery chip on Green Beret.
On both boards pin 19 is Wait_n and 13 is RD_n from the Z80.
I think that is everything I can figure out from the schematics. I guess I expected more TTL.
BTW, I happened to find this...work, but worth a try.
https://www.jammarcade.net/28-pin-cpld-replacement/
I guess using a CPLD/FPGA is an obvious idea. No details on what went inside the chip. It's from 2016, so maybe you can still contact the guy? The article talks about slowing the slew rate on the I/Os and the glitches were gone. Not sure that will
BTW, I might have made a logical mistake in the VHDL file.use of a high true output enable for OE.
OE <= (not s601) and FF1 and FF2 ;
Should be...
OE <= not s602_int ;
I was trying to write the same function as 602 but in a different way so the tools might not combine them (it's about the delay thing through the two inverters). But I don't think it will work and I goofed up the equation anyway. This way matches my
Delays are all in the chips in TTL, but in PLDs the delays happen in many parts of the circuit inside.
--
Rick C.
+-- Get 1,000 miles of free Supercharging
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of the "patch" board who had it working, so all is really ok. The Time Pilot board has the buses labeled the other way I just realized, so that's the source of the problem.I only see one part that might be the "patch board" for the custom chip, it's labeled "501" and "5C", not "3C".
3C is the location of the same '501' custom IC on the Time Pilot schematics
Now I'm confused about the buses. In the Green Beret schematic bus DB is on pins numbered 1 to 8 and bus D is on pins numbered 20 to 27. That is opposite your schematic for the internals. I suppose that was an error made by the original designer
Take my Kicad schematics as reference , some board use the entire functionality of the custom IC, some not.My TTL implementation is complete and has beeen succesfully tested on all boards.Labels may vary on different boards.giant mystery chip.
Pins 15 and 16 are not shown for the Green Beret. Your drawing shows them not connected. That seems ok.
These pins are used in other boards
Green Beret shows pin 18 going to the 200 pin mystery chip as an input. Any info on that guy? The signal is labeled "BUS".
In your schematic pin 17 is "603". The Green Beret has nothing connected if I understand the notation. Please confirm. On Time Pilot this is F2 and pin 12 connects to F3. I can't find the source of either. On Green Beret pin 12 is CS501 from the
Again, refer to my Kicad schematics for the reasons I explained above.on Time Pilot, from the giant mystery chip on Green Beret.
Pin 9 goes to the 2H signal on the Green Beret again from the giant mystery chip. On Time Pilot it is G2 from IC3, a small mystery chip. Also pin 10, G1 on Time Pilot is X15 on Green Beret, the CPU clock inverted. Pin 11 is the chip clock ~6 MHz
On both boards pin 19 is Wait_n and 13 is RD_n from the Z80.
I think that is everything I can figure out from the schematics. I guess I expected more TTL.
This '501' custom ICs can have different labels but it accomplishes same functions on all board at the end.
will work, but worth a try.
BTW, I happened to find this...
https://www.jammarcade.net/28-pin-cpld-replacement/
I guess using a CPLD/FPGA is an obvious idea. No details on what went inside the chip. It's from 2016, so maybe you can still contact the guy? The article talks about slowing the slew rate on the I/Os and the glitches were gone. Not sure that
I use a similar CPLD board made by me.That replacement on JAMMArcade site must be programmed with your code.Anyway, I already enable the SLOW SLEW RATE with your code but it didn't help.my use of a high true output enable for OE.
BTW, I might have made a logical mistake in the VHDL file.
OE <= (not s601) and FF1 and FF2 ;
Should be...
OE <= not s602_int ;
I was trying to write the same function as 602 but in a different way so the tools might not combine them (it's about the delay thing through the two inverters). But I don't think it will work and I goofed up the equation anyway. This way matches
Delays are all in the chips in TTL, but in PLDs the delays happen in many parts of the circuit inside.
OK, I'll try this code fix, thanks.
On Friday, 1 May 2020 16:24:23 UTC+2, Rick C wrote:dangerous if you don't have full control over it :)
I'm trying to understand what the circuit does. So when I ask about the signals and what they come from telling me to look at your design isn't giving me any info I don't already have.
Yes, sorry for upsetting you.Although I'm into electronics since many years I still have to fully understand it, that's the key to do electronics, I know.It's like a gorgeous woman, it bewitches and takes you but, like all beautiful things, it's
produce some delay as you said).Is this still correct given that the /OE is an active LOW signal?That's ok for now. Let's see if the code change helps or breaks it.
And you did it!It's working fine now also on Time Pilot PCB, no more watchdogging or other issues, congratulations.Just a question : you inverted in your latest code fix the /OE signal only one time whereas in my TTL schematics it's done twice (to
--
Rick C.
+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209
I'm trying to understand what the circuit does. So when I ask about the signals and what they come from telling me to look at your design isn't giving me any info I don't already have.
That's ok for now. Let's see if the code change helps or breaks it.
--
Rick C.
+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209
On Friday, 1 May 2020 16:24:23 UTC+2, Rick C wrote:dangerous if you don't have full control over it :)
I'm trying to understand what the circuit does. So when I ask about the signals and what they come from telling me to look at your design isn't giving me any info I don't already have.
Yes, sorry for upsetting you.Although I'm into electronics since many years I still have to fully understand it, that's the key to do electronics, I know.It's like a gorgeous woman, it bewitches and takes you but, like all beautiful things, it's
produce some delay as you said).Is this still correct given that the /OE is an active LOW signal?That's ok for now. Let's see if the code change helps or breaks it.
And you did it!It's working fine now also on Time Pilot PCB, no more watchdogging or other issues, congratulations.Just a question : you inverted in your latest code fix the /OE signal only one time whereas in my TTL schematics it's done twice (to
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