• simulation(error in loading design)

    From nivasregeti912@gmail.com@21:1/5 to All on Mon Apr 20 03:57:43 2020
    currently i'm doing a small code in verilog as a part of assignment.when i compiled the code,it ran sucessfully also the test bench file ran sucessfully.But the thing is when i click on simulation-->work ,in this work option i am not able to get my test
    bench file which is for simulation.Some one please help me with this.

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