• Is there a verilog syntax beginning with '$'?

    From Robert Willy@21:1/5 to All on Sat Sep 29 13:34:29 2018
    Hi, everyone:
    Verilog is not my daily design tool, but it is required a general familiarity in a job interview. I once noticed a verilog syntax beginning with '$'. I had found online forum discussing about it, but I can't remember the detail syntax now.

    Could you verilog expert tell me such a usage ('$____')?


    Thanks,

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  • From Robert Willy@21:1/5 to Robert Willy on Sat Sep 29 13:46:48 2018
    On Saturday, September 29, 2018 at 3:34:31 PM UTC-5, Robert Willy wrote:
    Hi, everyone:
    Verilog is not my daily design tool, but it is required a general familiarity in a job interview. I once noticed a verilog syntax beginning with '$'. I had found online forum discussing about it, but I can't remember the detail syntax
    now.

    Could you verilog expert tell me such a usage ('$____')?


    Thanks,

    Surely, it is not about $display, $write etc. It is a not usual usage, but I want to know it now.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Robert Willy@21:1/5 to Robert Willy on Sat Sep 29 21:03:43 2018
    On Saturday, September 29, 2018 at 3:34:31 PM UTC-5, Robert Willy wrote:
    Hi, everyone:
    Verilog is not my daily design tool, but it is required a general familiarity in a job interview. I once noticed a verilog syntax beginning with '$'. I had found online forum discussing about it, but I can't remember the detail syntax
    now.

    Could you verilog expert tell me such a usage ('$____')?


    Thanks,

    I got it. It is $signed. Thanks.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)