I need to find Postions of minimun and 2nd minimum in a row excluding zero
for example
[ 0 -3 2 1 5 8 ] min is 1 and 2nd min is 2 and position of minimum is 3
can anyone please help me to do it in verilog?
On Thursday, January 30, 2020 at 2:01:00 AM UTC-7, nitin sapre wrote:a time, and if it is smaller than either of the two minimum holding registers, replace one of the values.
I need to find Postions of minimun and 2nd minimum in a row excluding zero
for example
[ 0 -3 2 1 5 8 ] min is 1 and 2nd min is 2 and position of minimum is 3
can anyone please help me to do it in verilog?
This is all very dependent on how many clock cycles you have. If you have 6 clock cycles and can do this serially, you'd use a software algorithm: Start with two holding registers, each initialized with infinity, and then look at each sample, one at
If you have to do full-parallel, this becomes more difficult. Finding the minimum requires a binary tree; the location as well as the value is passed through each node of the tree. I had to create such a structure recently.
Finding the second-smallest value is more difficult in a full-parallel situation. You might look at the bitonic sort; this would sort all input values. You could just use the minimum two values and let the synthesizer prune the rest of the logic. I'm not sure if this is optimal, but it's probably close.
I don't know that it has to be a binary tree. In fact, a tree "feels" complex to me for such a simple problem. A more simple way to code this is a linear arrangement of compares. So a simple loop will generate the logic required. The only questionis whether this is in a clocked process or a combinatorial process. I'm not conversant in Verilog and am thinking in VHDL, so please correct me if there is no equivalent in Verilog.
question is whether this is in a clocked process or a combinatorial process. I'm not conversant in Verilog and am thinking in VHDL, so please correct me if there is no equivalent in Verilog.I don't know that it has to be a binary tree. In fact, a tree "feels" complex to me for such a simple problem. A more simple way to code this is a linear arrangement of compares. So a simple loop will generate the logic required. The only
If latency isn't a problem, then you could use a linear arrangement. For a recent design I had to find the minimum of 64 values (on every clock cycle), so had I used a linear arrangement that would have a delay of 64 compares, but if you use a binarytree it's a delay of log2(64)=6 compares. I ended up with a pipeline stage in the middle, so I did 3 levels of comparison in the first cycle and 3 levels in the second.
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