• median filter with verilog ?

    From Michael Kellett@21:1/5 to danielshalom431@gmail.com on Tue Aug 21 09:00:20 2018
    On 20/08/2018 18:23, danielshalom431@gmail.com wrote:
    Someone has an idea how to do it ?

    Is your problem with writing the Verilog, understanding the process or
    using Google ?

    There is a Wiki article that explains the basics and Google can find the OpenCores project written in Verilog.

    Why not define what you want to do, have a go at it and then come back
    and ask questions ?

    MK

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Y.V.V.Nagendra@21:1/5 to daniels...@gmail.com on Tue Aug 21 10:35:24 2018
    On Monday, August 20, 2018 at 10:53:11 PM UTC+5:30, daniels...@gmail.com wrote:
    Someone has an idea how to do it ?

    It seems you forget attaching the "it"!

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)