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Verilog Implementation of a Feed Forward Neural Network

By Victor Niga on Sun Apr 24 11:09:30 2022

Latest reply by mag on Thu Jun 23 21:55:59 2022
Read large MNIST file in System Verilog

By Haval Elias on Thu Jun 23 20:55:42 2022

Latest reply by Haval Elias on Thu Jun 23 20:55:42 2022
Pitfall with mixing of blocking and non-blocking assignments in SystemV

By okhajut on Sun Feb 20 14:05:20 2022

Latest reply by Kevin on Thu Jun 2 08:21:06 2022
By design, why does SystemVerilog logic type has 4-states possible but

By okhajut on Sun Feb 20 13:49:15 2022

Latest reply by Kevin on Thu Jun 2 08:14:15 2022
Bit Numbering in Verilog

By Tom Szolyga on Mon Oct 18 11:09:11 2021

Latest reply by Kevin on Thu Jun 2 08:08:36 2022
Issue with file operations in verilog

By GAYATHRI U on Fri May 27 04:56:57 2022

Latest reply by Gabor on Sun May 29 17:38:58 2022
Verilog Code for Parallel CRC encoding and Decoding using LFSR

By KRISHNA CHAITHANYA on Fri Apr 22 03:47:57 2022

Latest reply by Hariprasad Bhat on Sat Apr 30 23:58:21 2022
Up/Down Binary Counter with Dynamic Count-to Flag

By buse.victorstefan@decathlon.com on Sun Apr 21 15:33:31 2019

Latest reply by Beniamin Antal-Vaida on Mon Mar 28 08:58:19 2022
Accessing DUT internal signals in a SystemVerilog testbench

By okhajut on Sun Feb 20 14:47:34 2022

Latest reply by Anssi Saari on Tue Mar 22 16:47:51 2022
Verilog for Cyclone IV

By Tom Szolyga on Sun Sep 5 10:54:15 2021

Latest reply by okhajut on Sun Feb 20 14:07:24 2022
Verilog HDL Finite State Machine - Detecting decimal number

By Tanishk Singh on Sat Nov 6 21:56:17 2021

Latest reply by Richard Damon on Sun Nov 7 07:55:47 2021
VPI: How to walk hierarchy that contains generate blocks

By thomas jones on Tue Sep 28 08:07:38 2021

Latest reply by thomas jones on Tue Sep 28 08:07:38 2021
Re: How to use $time in verilog?

By Nawroz Qahraman on Fri Sep 24 06:20:55 2021

Latest reply by Nawroz Qahraman on Fri Sep 24 06:20:12 2021
verilog

By Niharika Behera on Fri Sep 3 23:06:11 2021

Latest reply by Richard Damon on Thu Sep 16 22:24:37 2021
Implementing PLDs (PAL/GAL) into Verilog

By briccus@gmail.com on Tue Aug 17 14:47:00 2021

Latest reply by Johann Klammer on Mon Sep 13 13:20:05 2021
How to build this MUX with sel=x?

By Mike Lyu on Tue Aug 3 12:24:05 2021

Latest reply by Richard Damon on Sun Aug 15 14:13:53 2021
Online source to learn System verilog.

By ATUL KUMAR on Thu May 20 10:07:34 2021

Latest reply by ATUL KUMAR on Thu May 20 10:07:34 2021
Calculating the average in Verilog

By smriti thakur on Tue May 18 22:37:47 2021

Latest reply by smriti thakur on Tue May 18 22:37:47 2021
Do unpacked arrays parse in the current icarus verilog?

By Johann Klammer on Sat Apr 3 16:48:13 2021

Latest reply by Johann Klammer on Sun Apr 4 09:07:42 2021
How to go to ASIC?

By Philipp Klaus Krause on Tue Nov 3 16:26:15 2020

Latest reply by stevem1 on Mon Dec 14 12:07:24 2020
It's Actually Verilog this time...

By Rick C on Thu Oct 22 11:44:56 2020

Latest reply by Kevin Neilson on Fri Oct 23 09:31:58 2020
Can you use a function to populate a ROM?

By silverace99@gmail.com on Mon Jan 13 16:03:40 2020

Latest reply by Gabor on Tue Oct 20 09:30:52 2020
May Have to Learn Verilog

By Rick C on Sat Oct 17 14:11:56 2020

Latest reply by Rick C on Mon Oct 19 10:33:44 2020
x's and don't cares in verilog?

By Muhmmad Elrabaa on Sat Oct 17 06:06:44 2020

Latest reply by Muhmmad Elrabaa on Sat Oct 17 06:06:44 2020
How powerful is Verilog at using parameters to specify designs?

By Kevin Simonson on Mon Sep 21 15:24:42 2020

Latest reply by Remigiusz Kaletka on Wed Oct 14 04:08:40 2020
almost_full/empty design in async fifo

By chenyong30000@gmail.com on Sun Jun 21 05:47:31 2020

Latest reply by Kevin Neilson on Tue Jun 23 12:32:32 2020
Determing change in signals.

By Nimesh Shahdadpuri on Sun Jun 14 12:09:30 2020

Latest reply by Rick C on Sun Jun 14 12:57:26 2020
initialize output nodes

By paslarerfan1@gmail.com on Fri Jun 12 10:30:49 2020

Latest reply by Rick C on Sat Jun 13 17:18:43 2020
how to simulate verilog with rom in modelsim?

By getdip43@gmail.com on Tue Jun 9 23:59:28 2020

Latest reply by getdip43@gmail.com on Tue Jun 9 23:59:28 2020
Open source 8b10b encoder/decoder, verilog

By vishaliit2016@gmail.com on Thu May 28 20:44:23 2020

Latest reply by Rick C on Fri Jun 5 06:31:29 2020
a wire by any other name

By TJ Edmister on Sat Apr 18 00:18:26 2020

Latest reply by EML on Sun May 17 09:54:32 2020
Verilog source code for Simple Bus Arbiter

By krishnan10497kmb@gmail.com on Fri Jan 18 02:24:36 2019

Latest reply by ukkalkarvijayalaxmi@gmail.com on Fri May 8 02:50:42 2020
always_comb behaviour not as I expect

By davew on Mon May 4 07:30:57 2020

Latest reply by davew on Mon May 4 07:30:57 2020
Bidirectional bus : how to in Verilog

By Rick C on Tue Apr 28 11:52:20 2020

Latest reply by Rick C on Fri May 1 12:25:28 2020
sign extension in Verilog 2001

By TJ Edmister on Mon Apr 13 16:32:33 2020

Latest reply by Rick C on Tue Apr 21 20:23:29 2020
simulation(error in loading design)

By nivasregeti912@gmail.com on Mon Apr 20 03:57:43 2020

Latest reply by nivasregeti912@gmail.com on Mon Apr 20 03:57:43 2020
Unknown condition in if statement is treated in what manner

By vishaliit2016@gmail.com on Thu Apr 2 07:49:39 2020

Latest reply by unfrostedpoptart on Sun Apr 5 15:35:33 2020
Open Source Silicon IP Survey

By mag on Fri Feb 28 10:23:22 2020

Latest reply by mag on Fri Feb 28 10:23:22 2020
storing a multiplexer output in memory depending on select line in veri

By nitin sapre on Mon Feb 17 01:27:48 2020

Latest reply by Rick C on Tue Feb 18 07:39:02 2020
how to find min and 2nd min and its positon in a row

By nitin sapre on Thu Jan 30 01:00:58 2020

Latest reply by Rick C on Wed Feb 12 12:05:16 2020
How to store a 11776x17408 matrix in verilog in form of RAM

By nitin sapre on Thu Jan 16 08:35:19 2020

Latest reply by nitin sapre on Wed Jan 29 22:12:53 2020
how to get the sign of each row in matrix

By nitin sapre on Thu Jan 23 20:15:14 2020

Latest reply by nitin sapre on Sat Jan 25 09:15:54 2020
to get sign of a matrix

By nitin sapre on Thu Jan 23 02:05:20 2020

Latest reply by Richard Damon on Fri Jan 24 11:20:02 2020
FYI: Verilog PDP-6 and PDP-10

By Lars Brinkhoff on Mon Jan 20 07:00:45 2020

Latest reply by Lars Brinkhoff on Mon Jan 20 07:00:45 2020
FSM Design in verilog using iverilog.

By Jatin Sharma on Thu Dec 26 08:16:35 2019

Latest reply by Gabor on Sun Dec 29 11:23:16 2019
Module Instantiation: How does Verilog identify an instantiated module?

By Otto Hunt on Wed Dec 11 18:57:06 2019

Latest reply by Otto Hunt on Thu Dec 12 19:30:04 2019
Book recommendations?

By Philipp Klaus Krause on Sat Nov 23 15:07:36 2019

Latest reply by Kevin Neilson on Mon Dec 2 10:19:04 2019
Systemverilog package shared var conflict

By Ron Liu on Tue Nov 26 20:04:19 2019

Latest reply by Ron Liu on Tue Nov 26 20:04:19 2019
Help running DDR3 simulation

By james.w.dalton@gmail.com on Sat Oct 12 08:47:28 2019

Latest reply by mag on Wed Oct 30 12:15:25 2019
[Fully Funded Scholarship] Research Assistantship (Spring, 2020) at the

By jg.lee on Mon Sep 23 00:22:12 2019

Latest reply by jg.lee on Mon Sep 23 00:22:12 2019
HDLC Clocking

By digitalguy33@gmail.com on Sat Aug 17 08:01:41 2019

Latest reply by Allan Herriman on Sun Aug 18 00:53:40 2019
? How to convert .lib to .v

By nag.gadireddy@gmail.com on Wed Jun 12 16:42:43 2019

Latest reply by nag.gadireddy@gmail.com on Wed Jun 12 16:42:43 2019
Safe State Machine with Conditional Statements in default clause.

By digitalguy33@gmail.com on Fri May 31 18:31:06 2019

Latest reply by digitalguy33@gmail.com on Fri May 31 18:31:06 2019
Is there an open source software or Python package can simulate Verilog

By Xiabing Lou on Thu May 30 11:46:06 2019

Latest reply by Xiabing Lou on Thu May 30 11:46:06 2019
verilog version for the SLAVE SD

By pini@rachip.com on Mon May 27 23:25:18 2019

Latest reply by pini@rachip.com on Mon May 27 23:25:18 2019
What meaning is '-' in '(((i-1)*3 + (j-1)) * 18)+17 -:18'?

By bookbaak87@gmail.com on Mon Apr 22 02:09:46 2019

Latest reply by bookbaak87@gmail.com on Mon Apr 22 02:09:46 2019
Is comp.lang.verilog dead? Is there an archive?

By EML on Sat Apr 6 01:46:00 2019

Latest reply by gnuarm.deletethisbit@gmail.com on Sat Apr 6 13:04:30 2019
Leafnode placeholder for group comp.lang.verilog

By gnuarm.deletethisbit@gmail.com on Mon Feb 25 07:34:20 2019

Latest reply by gnuarm.deletethisbit@gmail.com on Mon Feb 25 07:34:20 2019
Median filter in Verilog

By velamalaappu111@gmail.com on Mon Jan 28 09:03:16 2019

Latest reply by velamalaappu111@gmail.com on Mon Jan 28 09:03:16 2019
UVM on FPGA

By kadarshankumar@gmail.com on Sun Jan 6 22:50:20 2019

Latest reply by HT-Lab on Tue Jan 8 20:24:26 2019
Question about vlog

By hssig on Tue Dec 18 03:30:43 2018

Latest reply by hssig on Tue Dec 18 03:30:43 2018
Minimum time execution for APB operation.

By MJ on Fri Dec 7 01:15:10 2018

Latest reply by Richard Damon on Fri Dec 7 06:41:11 2018
Can you help me solve this Verilog problem ?

By Amartya Saikia on Mon Nov 5 06:34:16 2018

Latest reply by Amartya Saikia on Tue Nov 6 04:59:19 2018
always vs assign

By muhammad.comsats@gmail.com on Mon Nov 5 23:40:00 2018

Latest reply by muhammad.comsats@gmail.com on Mon Nov 5 23:40:00 2018
System Verilog issues with part_select/ generate simple for loop in alw

By ravichandar.a@gmail.com on Thu Nov 1 19:05:45 2018

Latest reply by Kevin Neilson on Mon Nov 5 09:00:19 2018
Viewing multi-dimensional arrays in Simvision

By ashishsharma.5790@gmail.com on Sun Oct 28 23:12:53 2018

Latest reply by ashishsharma.5790@gmail.com on Sun Oct 28 23:12:53 2018
Verilog template for template engine

By Bobby on Sun Oct 28 17:46:58 2018

Latest reply by Bobby on Sun Oct 28 17:46:58 2018
how to run package in vcs ?

By Ram on Mon Oct 15 03:46:28 2018

Latest reply by Ram on Mon Oct 15 03:46:28 2018
SystemVerilog is extend to verilog?

By Nasrin Eshraghi on Mon Oct 1 05:40:25 2018

Latest reply by dsc on Sat Oct 13 00:19:00 2018
IS there any open-sourse tool to convert SystemVerilog to Verilog?

By Nasrin Eshraghi on Fri Oct 12 07:50:50 2018

Latest reply by dsc on Sat Oct 13 00:05:01 2018
Are there any Free Verilog Simulators for Students???

By misterdavid218@gmail.com on Wed Oct 10 13:49:40 2018

Latest reply by gnuarm.deletethisbit@gmail.com on Wed Oct 10 17:54:15 2018
Is there a verilog syntax beginning with '$'?

By Robert Willy on Sat Sep 29 13:34:29 2018

Latest reply by Robert Willy on Sat Sep 29 21:03:43 2018
Could you explain the detail of this nonblocking?

By Robert Willy on Sun Sep 23 19:18:58 2018

Latest reply by Robert Willy on Sat Sep 29 13:29:31 2018
Writing a VCD to toggle-count generator in Python

By artemismohseni@gmail.com on Fri Sep 21 03:52:46 2018

Latest reply by artemismohseni@gmail.com on Fri Sep 21 07:00:13 2018
Import package error

By nikhil777nix@gmail.com on Fri Sep 7 01:51:55 2018

Latest reply by Y.V.V.Nagendra on Sat Sep 8 00:05:08 2018
Java or Python parser for System Verilog testbench ?

By Bobby on Sat Sep 1 15:56:24 2018

Latest reply by Petter Gustad on Wed Sep 5 21:50:29 2018
median filter with verilog ?

By Michael Kellett on Tue Aug 21 09:00:20 2018

Latest reply by Y.V.V.Nagendra on Tue Aug 21 10:35:24 2018