To help new users get started we have now made available, free of charge, a disk image and Verilog bitstream files specifically to run the Project Oberon Workstation on the Pepino LX9 FPGA development board 'out-of-the-box'.

This release is based on the very latest Oberon sources (July 2018) and Verilog sources (Jun 2018) as described in An Update of the RISC5 Implementation, by Niklaus Wirth 15.6.2018:

https://www.inf.ethz.ch/personal/wirth/

Project Oberon. (2013 Edition)
RISC5 Update

The system also includes our enhancements:

* Support for Numeric / Character CASE statements in the compiler
* Optional real-time clock devices
* Timestamps on uploaded files
* The additional high-capacity file system HCFiler
* Additional source code examples

The entire source code of the system, including the compiler, is included on the disk image. Go to

www.astrobe.com/RISC5/Workstation

for more details and to request a copy of the system,

Regards,
Chris Burrows
CFB Software
http://www.astrobe.com

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