• Std_logic_vector assignment with variable length

    From taylor.cj39@gmail.com@21:1/5 to All on Fri Mar 6 09:17:11 2020
    Hello good people of google,

    I am trying to assign a certain part of a SLV(std_logic_vector) to another shorter SLV, and forcing the remaining to be '0'.

    Ex, lets assign the middle 5 bits of big_word to small word.
    --

    Signal big_word :std_logic_vector(10 - 1 downto 0) := (others => '0');
    Signal small_word :std_logic_vector(5 - 1 downto 0) := (others => '0');

    ...
    Begin

    -- I can of course use this, but this is not very elegant for large SLVs Big_word <= "000" & small_word & "00";

    --I would like to do something more like:
    Big_word <= (7 -1 downto 2 => small_word, others => '0');
    --The tool I am using (vivado 2018.3) complains about small_word not being of type std_ulogic. Well the word is larger than 1 bit, so that is an issue.

    --
    My constraints are:
    VHDL '87
    Using ieee.std_logic_1164.all
    Using ieee.numeric_std
    Make this assignment in 1 line

    I really appreciate the help
    CT

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  • From Rick C@21:1/5 to All on Fri Mar 6 12:48:29 2020
    On Friday, March 6, 2020 at 12:17:15 PM UTC-5, CT wrote:
    Hello good people of google,

    I am trying to assign a certain part of a SLV(std_logic_vector) to another shorter SLV, and forcing the remaining to be '0'.

    Ex, lets assign the middle 5 bits of big_word to small word.
    --

    Signal big_word :std_logic_vector(10 - 1 downto 0) := (others => '0');
    Signal small_word :std_logic_vector(5 - 1 downto 0) := (others => '0');

    ...
    Begin

    -- I can of course use this, but this is not very elegant for large SLVs Big_word <= "000" & small_word & "00";

    --I would like to do something more like:
    Big_word <= (7 -1 downto 2 => small_word, others => '0');
    --The tool I am using (vivado 2018.3) complains about small_word not being of type std_ulogic. Well the word is larger than 1 bit, so that is an issue.

    If this is being done in a process you can always do it with two assignments.

    Big_word <= (others => '0');
    Big_word (7 -1 downto 2) <= small_word;

    --

    Rick C.

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  • From CT@21:1/5 to All on Fri Mar 6 18:16:58 2020
    Rick,

    Thanks for the input.

    I have done this in a process before with the method you mentioned.

    Do you know of a 1 or 2 lines solution when NOT in a process?

    CT

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  • From Rick C@21:1/5 to All on Fri Mar 6 19:17:05 2020
    On Friday, March 6, 2020 at 9:17:01 PM UTC-5, CT wrote:
    Rick,

    Thanks for the input.

    I have done this in a process before with the method you mentioned.

    Do you know of a 1 or 2 lines solution when NOT in a process?

    CT

    I would have expected your original solution to have worked. I believe this was only supported once VHDL-2008 came out. Is your tool set for 2008? Often this has to be enabled since by default tools frequently don't support these "modern extensions".
    Or it is possible it is simply not supported.

    Oh, wait! I see in your original post you are limited to VHDL '87. So there's the rub!

    Doulos is a great source of info on issues like this. Here is a page talking about the 2008 extensions.

    https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/

    Search down the page for "Vectors in aggregates". They explain this was only added in 2008. What tool are you using? I would be hard pressed to use a tool that is so out of sync with the real world.

    --

    Rick C.

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  • From CT@21:1/5 to All on Sat Mar 7 06:56:21 2020
    Rick,

    I am using vivado 2018.3. I believe it is defaulted to VHDL 87. I will look into upgrading to 08. I'm still green here, and wanted to write my design in a way that could be used in as many places as possible. VHDL 08 is supported most everywhere you say?
    I'll have to do some reading up on this.

    That link is a great resource, I will keep that in mind.

    Thanks again

    CT

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  • From Rick C@21:1/5 to All on Sat Mar 7 09:46:06 2020
    On Saturday, March 7, 2020 at 9:56:24 AM UTC-5, CT wrote:
    Rick,

    I am using vivado 2018.3. I believe it is defaulted to VHDL 87. I will look into upgrading to 08. I'm still green here, and wanted to write my design in a way that could be used in as many places as possible. VHDL 08 is supported most everywhere you
    say? I'll have to do some reading up on this.

    That link is a great resource, I will keep that in mind.

    Thanks again

    CT

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug901-vivado-synthesis.pdf

    Chapter 5, page 177.

    https://www.xilinx.com/support/answers/62005.html

    --

    Rick C.

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  • From Rick C@21:1/5 to All on Mon Mar 9 14:39:01 2020
    On Saturday, March 7, 2020 at 9:56:24 AM UTC-5, CT wrote:
    Rick,

    I am using vivado 2018.3. I believe it is defaulted to VHDL 87. I will look into upgrading to 08. I'm still green here, and wanted to write my design in a way that could be used in as many places as possible. VHDL 08 is supported most everywhere you
    say? I'll have to do some reading up on this.

    That link is a great resource, I will keep that in mind.

    Thanks again

    CT

    Do us a favor and report back once you have found a solution to your problem. It's nice to learn what you've found out.

    --

    Rick C.

    -+ Get 1,000 miles of free Supercharging
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  • From CT@21:1/5 to All on Wed Mar 11 08:01:49 2020
    Unfortunately even with vhdl 08 the solution:

    Big_word <= (7 -1 downto 2 => small_word, others => '0');

    Does not work. When this is used, the whole big_word signal is assigned to '0'.

    I will keep trying with vhdl 08 and report back once ive found a solution

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  • From Rob Gaddi@21:1/5 to All on Wed Mar 11 09:27:15 2020
    On 3/11/20 8:01 AM, CT wrote:
    Unfortunately even with vhdl 08 the solution:

    Big_word <= (7 -1 downto 2 => small_word, others => '0');

    Does not work. When this is used, the whole big_word signal is assigned to '0'.

    I will keep trying with vhdl 08 and report back once ive found a solution


    Slices like that only operate with single bit values.

    You can write it as a function or procedure though. That way you can do sequential assignment.

    function pad_right(val:std_logic_vector, len:integer) return std_logic_vector is
    variable x : std_logic_vector(len-1 downto 0) := (others => '0');
    begin
    x(len-1 downto len-(val'length)) := val;
    return x;
    end function pad_right;

    big_word <= pad_right(small_word, big_word'length);

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  • From Rick C@21:1/5 to Rob Gaddi on Wed Mar 11 10:13:20 2020
    On Wednesday, March 11, 2020 at 12:27:19 PM UTC-4, Rob Gaddi wrote:
    On 3/11/20 8:01 AM, CT wrote:
    Unfortunately even with vhdl 08 the solution:

    Big_word <= (7 -1 downto 2 => small_word, others => '0');

    Does not work. When this is used, the whole big_word signal is assigned to '0'.

    I will keep trying with vhdl 08 and report back once ive found a solution


    Slices like that only operate with single bit values.

    Can you explain what you mean by "slices like that"??? Like what?

    Here is a hard to find example of exactly the slice aggregate operation the OP is talking about.

    https://books.google.com/books?id=ETxLguPMEY0C&pg=PA166&lpg=PA166&dq=VHDL+slice+in+an+array+aggregate&source=bl&ots=q9wZSq_TB_&sig=ACfU3U3hcaEpAlXpDSw93ilUOjLnmPUIHg&hl=en&sa=X&ved=2ahUKEwiMm9DE75LoAhX1mXIEHXgcDKEQ6AEwBnoECAgQAQ#v=onepage&q=VHDL%20slice%
    20in%20an%20array%20aggregate&f=false

    Scroll down to p167.


    You can write it as a function or procedure though. That way you can do sequential assignment.

    function pad_right(val:std_logic_vector, len:integer) return std_logic_vector is
    variable x : std_logic_vector(len-1 downto 0) := (others => '0');
    begin
    x(len-1 downto len-(val'length)) := val;
    return x;
    end function pad_right;

    big_word <= pad_right(small_word, big_word'length);

    The function suggestion might be the best to get past the issue and get the work done.

    --

    Rick C.

    +- Get 1,000 miles of free Supercharging
    +- Tesla referral code - https://ts.la/richard11209

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  • From Rob Gaddi@21:1/5 to Rick C on Wed Mar 11 12:45:08 2020
    On 3/11/20 10:13 AM, Rick C wrote:
    On Wednesday, March 11, 2020 at 12:27:19 PM UTC-4, Rob Gaddi wrote:
    On 3/11/20 8:01 AM, CT wrote:
    Unfortunately even with vhdl 08 the solution:

    Big_word <= (7 -1 downto 2 => small_word, others => '0');

    Does not work. When this is used, the whole big_word signal is assigned to '0'.

    I will keep trying with vhdl 08 and report back once ive found a solution >>>

    Slices like that only operate with single bit values.

    Can you explain what you mean by "slices like that"??? Like what?

    Here is a hard to find example of exactly the slice aggregate operation the OP is talking about.

    https://books.google.com/books?id=ETxLguPMEY0C&pg=PA166&lpg=PA166&dq=VHDL+slice+in+an+array+aggregate&source=bl&ots=q9wZSq_TB_&sig=ACfU3U3hcaEpAlXpDSw93ilUOjLnmPUIHg&hl=en&sa=X&ved=2ahUKEwiMm9DE75LoAhX1mXIEHXgcDKEQ6AEwBnoECAgQAQ#v=onepage&q=VHDL%
    20slice%20in%20an%20array%20aggregate&f=false

    Scroll down to p167.


    You can write it as a function or procedure though. That way you can do
    sequential assignment.

    function pad_right(val:std_logic_vector, len:integer) return std_logic_vector is
    variable x : std_logic_vector(len-1 downto 0) := (others => '0');
    begin
    x(len-1 downto len-(val'length)) := val;
    return x;
    end function pad_right;

    big_word <= pad_right(small_word, big_word'length);

    The function suggestion might be the best to get past the issue and get the work done.


    You're right. Per 9.3.3.3 of the 2008 LRM:

    ---
    For an element association with a choice that is a discrete range and an expression of the element type of the aggregate, the value of the expression is the element at each index value in the range.

    For an element association with a choice that is a discrete range and an expression of the type of the aggregate, each element of the value of the expression is the value of the element of the aggregate at the matching index value in the range.
    ---

    I don't think I've ever trusted that a tool was going to implement this properly.

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  • From CT@21:1/5 to All on Thu Mar 12 11:23:09 2020
    Thanks guys,

    Youve helped me find a solution that fits my very specific requirements. Seeing as that you guys are definitely more experienced than I, and it dosen't seem like you use the method I am trying to do very frequently, what methods do you prefer for this
    task (assigning a part of a slv to another slv, the rest '0')?

    Using the function Rob used? Or always making this sort of assignment in a combinational process?

    CT

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  • From Rick C@21:1/5 to All on Thu Mar 12 11:35:40 2020
    On Thursday, March 12, 2020 at 2:23:12 PM UTC-4, CT wrote:
    Thanks guys,

    Youve helped me find a solution that fits my very specific requirements. Seeing as that you guys are definitely more experienced than I, and it dosen't seem like you use the method I am trying to do very frequently, what methods do you prefer for this
    task (assigning a part of a slv to another slv, the rest '0')?

    Using the function Rob used? Or always making this sort of assignment in a combinational process?

    Unless it were part of a conditional, what would be the value of assigning part of an array permanently to zero? In a conditional this could be used since the '0' parts might have other values for other input combinations. But in a simple assignment
    the '0' parts would always be zero. In that case I likely would have three concurrent assignment statements, one each for the left and right zeros and one for the variable part.

    I don't use functions very often unless they are part of a library with potential reuse. Likely I just never developed the habit. It's not like the modularization isn't useful.

    --

    Rick C.

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