Hi,

Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle:

1.
p1: process(CLK) is
begin
if CLK'event and CLK = '1' then
if C1 then
An_Array(a) <= D1;
end if;

-- I know a /= b
-- do I need to inform VHDL compiler of 2 different addresses?
if C2 then
An_Array(b) <= D2;
end if;
end if;
end process;

2.
p2: process(CLK) is
begin
if CLK'event and CLK = '1' then
case C1 & C2 is
when "10" =>
An_Array(a) <= D1;

when "01" =>
An_Array(b) <= D2;

when "11" =>
-- I know a /= b
-- do I need to inform VHDL compiler of 2 different addresses?
An_Array(a) <= D1;
An_Array(b) <= D2;

when others =>
null;
end case;
end if;
end process;

I think it is no problem with a simulator.

Thank you.

Weng

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On 2019-09-24 13:51, Weng Tianxiang wrote:

Hi,

Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle:

1.
p1: process(CLK) is
begin
if CLK'event and CLK = '1' then
if C1 then
An_Array(a) <= D1;
end if;

-- I know a /= b
-- do I need to inform VHDL compiler of 2 different addresses?
if C2 then
An_Array(b) <= D2;
end if;
end if;
end process;

2.
p2: process(CLK) is
begin
if CLK'event and CLK = '1' then
case C1 & C2 is
when "10" =>
An_Array(a) <= D1;

when "01" =>
An_Array(b) <= D2;

when "11" =>
-- I know a /= b
-- do I need to inform VHDL compiler of 2 different addresses?
An_Array(a) <= D1;
An_Array(b) <= D2;

when others =>
null;
end case;
end if;
end process;

I think it is no problem with a simulator.

Thank you.

Weng

What you are trying to create is a 2-port array. If your target
technology provides it, this is normally done by instantiating a 2-port
RAM macro. If you are trying to synthesize a 2-port array then I think
your process p1 is an adequate description. The second is just a more complicated way of saying the same thing. I don't think you need to
give any special instructions to the synthesis tool to tell it that a /=
b when C1 and C2 are active at the same time. The tool should just
create an AND-OR Mux for every memory location. There will exist a
logical possibility of an address collision but that shouldn't be a
problem if a /= b when both C1 and C2 are active.

Charles Bailey

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, September 27, 2019 at 12:25:31 AM UTC-4, Charles Bailey wrote:

On 2019-09-24 13:51, Weng Tianxiang wrote:

Hi,

Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle:

1.
p1: process(CLK) is
begin
if CLK'event and CLK = '1' then
if C1 then
An_Array(a) <= D1;
end if;

-- I know a /= b
-- do I need to inform VHDL compiler of 2 different addresses?
if C2 then
An_Array(b) <= D2;
end if;
end if;
end process;

2.
p2: process(CLK) is
begin
if CLK'event and CLK = '1' then
case C1 & C2 is
when "10" =>
An_Array(a) <= D1;

when "01" =>
An_Array(b) <= D2;

when "11" =>
-- I know a /= b
-- do I need to inform VHDL compiler of 2 different addresses?
An_Array(a) <= D1;
An_Array(b) <= D2;

when others =>
null;
end case;
end if;
end process;

I think it is no problem with a simulator.

Thank you.

Weng

What you are trying to create is a 2-port array. If your target
technology provides it, this is normally done by instantiating a 2-port
RAM macro. If you are trying to synthesize a 2-port array then I think
your process p1 is an adequate description. The second is just a more complicated way of saying the same thing. I don't think you need to
give any special instructions to the synthesis tool to tell it that a /=
b when C1 and C2 are active at the same time. The tool should just
create an AND-OR Mux for every memory location. There will exist a
logical possibility of an address collision but that shouldn't be a
problem if a /= b when both C1 and C2 are active.

Charles Bailey

If you consider the logic that would be created, it can't deal with both ports writing to the same address other than by giving one port priority, so obviously that is what will happen. The trick is doing what is appropriate in the cases where there is
no conflict. The hardware is not trivial.

Luckily I work with FPGAs rather than custom designs and the hardware is provided by the manufacturers. So the appropriate HDL will easily infer the appropriate hardware. Easy-peasy.

--

Rick C.

- Get 2,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

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