I have created a register file that holds 4 32 bit registers.Now i would like to check whether the first 3 bits of the first register(CTL) is 1 and then check if the 1st bit of 2nd register is 1 .If so the BC_en bit should go high.....which is nothappening....can anyone please see the code below and help me?
............................................................................ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std_UNSIGNED.ALL;
entity cntrregFile is
port
(
input : in std_logic_vector (31 downto 0);
writeEnable : in std_logic;
clk : in std_logic;
readregSel : in std_logic_vector (2 downto 0);
writeregSel : in std_logic_vector (2 downto 0);
readEnable : in std_logic;
output : out std_logic_vector (31 downto 0);
bc_en : out std_logic
);
end cntrregFile;
architecture behavioral of cntrregFile is
type registerFile is array(0 to 3) of std_logic_vector(31 downto 0);
signal registers : registerFile;
signal CTL : std_logic_vector(31 downto 0);
signal BC_CTL : std_logic_vector(31 downto 0);
signal BC_FIFO_CTL : std_logic_vector(31 downto 0);
signal ENCDEC_CTL : std_logic_vector(31 downto 0);
begin
process (clk,writeregSel,writeEnable,readregSel,readEnable) is
begin
if (rising_edge(clk) and writeEnable='1' ) then
if ( writeregSel="000") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="001") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="010") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="011") then
registers (to_integer(writeregSel)) <= input ;
end if;
elsif (rising_edge(clk) and readEnable='1') then
if (readregSel="000") then
CTL <= registers(to_integer(readregSel));
output <= CTL;
elsif(readregSel="001") then
BC_CTL <= registers(to_integer(readregSel));
output<= BC_CTL;
elsif(readregSel="010") then
BC_FIFO_CTL <= registers(to_integer(readregSel));
output<= BC_FIFO_CTL;
elsif(readregSel="011") then
ENCDEC_CTL <= registers(to_integer(readregSel));
output<=ENCDEC_CTL ;
end if;
end if;
end process;
process (clk,CTL,BC_CTL) is
begin
if (CTL(0)= '1') and (CTL(1)='1') and
(CTL(2)='0') and (CTL(3)='0')then
if (BC_CTL(0) ='1') then
bc_en<= '1';
else
bc_en<='0';
end if;
end if;
end process;
end behavioral;
On Thursday, February 6, 2020 at 6:29:01 AM UTC-5, sweety...@gmail.com wrote:happening....can anyone please see the code below and help me?
I have created a register file that holds 4 32 bit registers.Now i would like to check whether the first 3 bits of the first register(CTL) is 1 and then check if the 1st bit of 2nd register is 1 .If so the BC_en bit should go high.....which is not
reset, that too. But only if the reset or any other signal is asynchronous. So clean up your sensitivity list and your simulations will run faster.
............................................................................ >> library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std_UNSIGNED.ALL;
entity cntrregFile is
port
(
input : in std_logic_vector (31 downto 0);
writeEnable : in std_logic;
clk : in std_logic;
readregSel : in std_logic_vector (2 downto 0);
writeregSel : in std_logic_vector (2 downto 0);
readEnable : in std_logic;
output : out std_logic_vector (31 downto 0);
bc_en : out std_logic
);
end cntrregFile;
architecture behavioral of cntrregFile is
type registerFile is array(0 to 3) of std_logic_vector(31 downto 0);
signal registers : registerFile;
signal CTL : std_logic_vector(31 downto 0);
signal BC_CTL : std_logic_vector(31 downto 0);
signal BC_FIFO_CTL : std_logic_vector(31 downto 0);
signal ENCDEC_CTL : std_logic_vector(31 downto 0);
begin
process (clk,writeregSel,writeEnable,readregSel,readEnable) is
begin
if (rising_edge(clk) and writeEnable='1' ) then
if ( writeregSel="000") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="001") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="010") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="011") then
registers (to_integer(writeregSel)) <= input ;
end if;
elsif (rising_edge(clk) and readEnable='1') then
if (readregSel="000") then
CTL <= registers(to_integer(readregSel));
output <= CTL;
elsif(readregSel="001") then
BC_CTL <= registers(to_integer(readregSel));
output<= BC_CTL;
elsif(readregSel="010") then
BC_FIFO_CTL <= registers(to_integer(readregSel));
output<= BC_FIFO_CTL;
elsif(readregSel="011") then
ENCDEC_CTL <= registers(to_integer(readregSel));
output<=ENCDEC_CTL ;
end if;
end if;
end process;
process (clk,CTL,BC_CTL) is
begin
if (CTL(0)= '1') and (CTL(1)='1') and
(CTL(2)='0') and (CTL(3)='0')then
if (BC_CTL(0) ='1') then
bc_en<= '1';
else
bc_en<='0';
end if;
end if;
end process;
end behavioral;
A couple of small issues that aren't your problem. A clocked process only needs the signals in the sensitivity list that are prerequisites to any of the outputs changing. So it should include the clock signal and if you had an async input such as
Then by convention there is an outer conditional to detect the rising edge of the clock and all other logic is inside this structure as separate conditionals. I can't say this causes any problems, but I've never seen anyone do it in two separateconditionals so I can't say for sure. But it will be easier to get help if your code has the same basic structure as everyone else's.
Your use of IEEE.STD_LOGIC_UNSIGNED along with ieee.numeric_std_UNSIGNED has several problems. The former is deprecated and you should stop using it. The latter is not even a thing... the name is ieee.numeric_std. It includes both signed andunsigned types.
Another style issue which may be causing a failure (not sure) is with writing the registers. You are using a conditional to decode the register select, then you are addressing the register directly by turning writeregSel into an integer. You onlyneed to do one of those things, not both.
There is a mismatch with the number of registers (4) and the possible registers selected by the select lines (8 or 3 depending on whether or not they are 1-hot). So which is right?saying this is wrong, I just want to make sure you have it right from the assignment.
Do you realize that when reading you have a register delay between the read enable and the register value being saved in CTL, BC_CTL, BC_FIFO_CTL and ENCDEC_CTL? Then you add another register delay before assigning those values to output? I'm not
The register delays can be important to your application and in particular to the decoding. Right now the decode is on the registers CTL and BC_CTL while you are also storing the data in the register file "registers". registers is updated when youwrite the register file. CTL and BC_CTL are only written when you read the register file.
So I think you have many errors in your code that are logical errors. I suggest that you try drawing a block diagram of the logic you would use to implement this design. Show the registers, data flow and decodes. Then you can write code to describethat structure and it should be a closer match.
It's very useful to have your own libraries that you can easily port between projects. The only problem with this is that every tool seems to expect you to put your code in a directory structure they create for your project rather than putting alltheir stuff in a sub-directory under yours to keep it out of sight, out of mind. So these library files often get copied around rather than trying to point back to another file outside of the project directory.
On Wednesday, February 12, 2020 at 10:13:33 AM UTC-5, Rick C wrote:their stuff in a sub-directory under yours to keep it out of sight, out of mind. So these library files often get copied around rather than trying to point back to another file outside of the project directory.
It's very useful to have your own libraries that you can easily port between projects. The only problem with this is that every tool seems to expect you to put your code in a directory structure they create for your project rather than putting all
If you use version control such as Subversion and of course many others, then the true master copy of the file is inside that version control system, not in some other folder on your hard drive. Each individual project would reference the source fromversion control and place it where the tool is happy about it. No need to reference source files that are in some other folder.
Kevin Jennings
Thankyou so much everyone for replying. I've made some changes to my code as you all have suggested and now its working perfectly.
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