On Monday, December 2, 2019 at 12:14:44 PM UTC-5, silve...@gmail.com wrote:
- Can you post the entity definition for 'ila' and the exact compiler error message?
- Assuming that 'probe0' consists of more bits than just '31 downto 11', where are the other bits being mapped? If probe0 does not have any more bits, then why are you port mapping to 'probe0(31 downto 11)' instead of just 'probe0'?
Kevin Jennings
On Monday, December 2, 2019 at 1:13:05 PM UTC-5, silve...@gmail.com wrote: You posted the component declaration but not the entity declaration for ila. They probably look nearly identical except for 'entity' vs 'component', but please post the entity as well since sometimes the two are different and a cause for compilererrors.
As a side note, since you are using direct entity instantiation (i.e. "ila_inst: entity work.ila(rtl)"), you don't need any component declaration. Components are only needed when you don't have the source code for a particular entity, usually becauseit is coming from some pre-compiled library from a vendor or something. This is off topic, but thought you might find it useful.
You say that probe0 is entirely mapped but what you showed for the mapping is in comments, not live code.map which I think would produce the error message that you described. However, if it is still not compiling, you will need to post the following posted to diagnose:
One line that looks suspicious is "probe0( 8 downto 0) => std_logic_vector(SIG_C)". Since SIG_A and SIG_B are one bit signals, does that mean SIG_C is as well? If it is, then you're trying to map a single bit signal to a nine bit vector in the port
- The entity definition for ila
- The full port map in the instantiation of ila
- Declarations of all signals that are included in the port mapping (i.e. SIG_A, SIG_B, SIG_C, etc.)
You didn't post the error message from Modelsim either. Since that error message will refer to a line number in your source file, you will also need to let us know exactly which line is being pointed to by Modelsim.
Kevin Jennings
I don't see anything wrong with what you have posted, maybe it is some peculiarity about the Verilog to VHDL interface or maybe a tool bug. If you have paid support open a ticket. Didn't have time to put it in and play with it on my own.
For a workaround, you could define a zero vector constant like this
constant Zero: std_logic_vector(31 down to 0) := (others => '0');
Then on the port map take out an appropriate size slice to attach to the port.
Kevin Jennings
On Tuesday, December 3, 2019 at 5:23:10 PM UTC-7, KJ wrote:
I don't see anything wrong with what you have posted, maybe it is some peculiarity about the Verilog to VHDL interface or maybe a tool bug. If you have paid support open a ticket. Didn't have time to put it in and play with it on my own.
For a workaround, you could define a zero vector constant like this
constant Zero: std_logic_vector(31 down to 0) := (others => '0');
Then on the port map take out an appropriate size slice to attach to the port.
Kevin Jennings
Thanks for the suggestion; I used that workaround and while it looks janky, at least it works. Could certainly be a tool issue; I'll consult our modelsim rep about it.
Cheers,
Stephen
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