I have some code that fails in the simulator but seemingly is OK when synthesized:
Apparently the simulator thinks I am assigning two values to one destination. I try to assign to part of "shifter" outside of the
process and the rest of it inside of the process. In VHDL, is the
array considered one signal, or is it a convenience to describe a multiplicity of independent signals? Is my original code incorrect?
On Saturday, September 2, 2023 at 4:55:01 PM UTC-4, littlewing wrote:t matter that the two processes assigned to non-overlapping sub-elements of the signal 'shifter'.
I have some code that fails in the simulator but seemingly is OK when
synthesized:
Apparently the simulator thinks I am assigning two values to one
destination. I try to assign to part of "shifter" outside of the
process and the rest of it inside of the process. In VHDL, is the
array considered one signal, or is it a convenience to describe a
multiplicity of independent signals? Is my original code incorrect?
VHDL considers a signal to be driven if it is the target of an assignment. In this case, the signal 'shifter' (all bits) is being driven both by your process with the sensitivity list as well as the implicit 'shifter(0) <= inval;' process . It doesn'
The reason for the 'X' is that while the sensitivity list process drives all the bits of 'shifter', since there is no assignment to 'shifter(0)' it should resolve to 'U' for that process. When it comes to resolving the two drivers for 'shifter(0)',the 'U' will win over anything that the 'shifter(0) <= inval;' process creates. Since you say that synthesis is OK, the synthesis tool is likely letting it slide for some reason. That tool then would not really be compliant even if it is doing what you
Your original code is not correct and that is what the simulator is effectively telling you when you run the simulation. 'Not correct' meaning that simulation results do not match synthesis results. It is not 'illegal' VHDL since VHDL does allowmultiple drivers to a 'resolved' signal type such as 'std_logic/std_logic_vector'.
However, most synthesis are for signals that are not meant to be driven by more than one driver. The better type to use for all of those signals is 'std_ulogic/std_ulogic_vector'. If you take your original code and change the type of 'shifter' from 'std_logic_vector' to 'std_ulogic_vector', Vivado should fail to compile because you have multiple drivers for 'shifter' and it should tell you that. The nice thing is that you won't have to run any simulation to figure that out. Std_logic is the 'usual'
Kevin Jennings
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