1. Forum
  2. Usenet
  3. COMP.LANG.VHDL

  • Insert transient voltage on internal signal of a module - Verilog

    From Raphael Viera@21:1/5 to All on Tue Oct 22 12:40:46 2019
    I have a verilog testbench in order to perform gate level simulation of a module. I want to inject a transient voltage at the output of specific gates inside the module but can't find a way to do it. I can insert transient voltages (like glitches) at the
    inputs (example below), but I need to inject on internal signals. Can anyone shed a light on the issue?

    Example: glitch in a clock signal (https://stackoverflow.com/questions/2251465/producing-a-clock-glitch-in-a-verilog-design)

    always begin: inject_clk_glitch
    #1 force clk = 1;
    #1 force clk = 0;
    #1 release clk;
    end

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From HT-Lab@21:1/5 to Raphael Viera on Fri Oct 25 10:38:45 2019
    On 22/10/2019 20:40, Raphael Viera wrote:


    I have a verilog testbench in order to perform gate level simulation of a module. I want to inject a transient voltage at the output of specific gates inside the module but can't find a way to do it. I can insert transient voltages (like glitches) at
    the inputs (example below), but I need to inject on internal signals. Can anyone shed a light on the issue?

    Example: glitch in a clock signal (https://stackoverflow.com/questions/2251465/producing-a-clock-glitch-in-a-verilog-design)

    always begin: inject_clk_glitch
    #1 force clk = 1;
    #1 force clk = 0;
    #1 release clk;
    end


    If you have access to Modelsim/Questa/Riviera have a look a look at
    signalspy which is more capable than Verilog/VHDL's force language
    construct. You could also look at the Tcl force command which has
    similar capabilities.

    Both should be able to force a signal/logic/etc in your netlist.

    Good luck,

    Hans
    www.ht-lab.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)