• Insert stimulus internal module signal

    From Raphael Viera@21:1/5 to All on Tue Oct 22 12:27:02 2019
    I have a verilog testbench in order to perform gate level simulation of a module. I want to inject a transient voltage at the output of specific gates inside the module but can't find a way to do it. I can of course insert transient voltages (like
    glitches) at the inputs (example below), but I need to inject on internal signals. Can anyone shed a light on the issue?

    Example: glitch in a clock signal

    always begin: voltage_transient
    #10 force clk = 1;
    #0.5 force clk = 0;
    #1 release clk;

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