Wouldn't that code be valid under the specification when you look at default binding indication?component declaration. Where an entity has more than one architecture, the last analysed architecture will be used."
For the VHDL 2000 standard which I just looked thru that would be Section 5.2.2.
The VHDL reference guide webpages (https://www.ics.uci.edu/~jmoorkan/vhdlref/confspec.html - I believe this site is for the 93 standard) sums it up nicely as follows:
"In the absence of an explicit configuration for any part of a model, default binding will occur. For each unbound instance of every component, an entity will be selected whose name, port names and port types etc. match those in the corresponding
This answer is not to imply that the current tools don't bend rules when it comes to following the written standard. I cannot answer with confidence if they do or don't.
Hi,
I have a better grasp of the question you are asking however, do you mind explaining how you get to this assertion you state as true using quotes of the standard to support the assertion:
"So the Root Declarative Region shouldn't contain 'e', and therefore according to the visibilty, scope etc. rules, 'e' shouldn't even be visible and the compiler should error and say so (by my interpretation of the LRM, at least)."
It would make the question more clear to me and perhaps to others. Specifically, I am interested as to how you think there would be no visibility of ''e" to the compiler.
On Tuesday, 31 May 2022 at 02:23:09 UTC+1, patel...@gmail.com wrote:unit until it has successfully parsed part of it? Surely this applies to all design units, primary & secondary.
Hi,
I have a better grasp of the question you are asking however, do you mind explaining how you get to this assertion you state as true using quotes of the standard to support the assertion:
"So the Root Declarative Region shouldn't contain 'e', and therefore according to the visibilty, scope etc. rules, 'e' shouldn't even be visible and the compiler should error and say so (by my interpretation of the LRM, at least)."
It would make the question more clear to me and perhaps to others. Specifically, I am interested as to how you think there would be no visibility of ''e" to the compiler.
Hi Patel,
Ok, here goes with my interpretation of the rules that matter for this case (from VHDL-2002 LRM):
10.1 "In addition to the above declarative regions, there is a root declarative region, not associated with a portion
of the text of the description, but encompassing any given primary unit. At the beginning of the analysis of a
given primary unit, there are no declarations whose scopes (see 10.2) are within the root declarative region."
So this is saying that when starting to parse a VHDL file, the root declarative region has no declarations. Seems pretty obvious. But this is supposed to apply to primary units - but how does the compiler know if it's looking at a primary or secondary
It says in 11.2:library) and everything in std.standard.* . Notably, this does not include any entities of the work library such as entity 'e' from my example.
"Every design unit except package STANDARD is assumed to contain the following implicit context items as
part of its context clause:
library STD, WORK ; use STD.STANDARD.all ;"
So this is how the predefined stuff gets into the root declarative region and is visible. Before the compiler gets to parsing any VHDL code, even context clauses, the root declarative region has only the following visible in it: std (library), work (
I believe that if a VHDL file has multiple design units, whether primary or secondary, parsing of each design unit begins with a fresh new root declarative region with nothing in it except the predefined stuff. So after 'end entity;' of my example, thecompiler begins a fresh new root declarative region (not containing 'e').
I haven't found any special case treatment of the entity_name of an architecture body in the LRM, so I conclude that in a literal interpretation of the rules, you should actually needThe library declarative region is mentioned in a couple of places in the LRM and nowhere else, so it's not exactly obvious what its purpose is or why the LRM even mentions it.
architecture a of work.e is -- OK: 'e' visible by selection
...
begin
...
end architecture;
OR
use work.e;
architecture a of e -- OK: 'e' made visible by use clause
...
begin
...
end architecture;
I guess that in most VHDL compilers, there is a special case where the entity_name lookup for an architecture body is not done within the root declarative region but instead goes to the library declarative region (which certainly does have 'e' visible).
On 2022-05-31 03:42, Tomas Whitlock wrote:*snip* for brevity
On Tuesday, 31 May 2022 at 02:23:09 UTC+1, patel...@gmail.com wrote:
visible). The library declarative region is mentioned in a couple of places in the LRM and nowhere else, so it's not exactly obvious what its purpose is or why the LRM even mentions it.I guess that in most VHDL compilers, there is a special case where the entity_name lookup for an architecture body is not done within the root declarative region but instead goes to the library declarative region (which certainly does have 'e'
The WORK library is always visible without it needing to be declared.
Entity 'e' was compiled into library WORK so it is visible when the architecture is compiled. I've never seen the USE statement used for anything other than pulling in packages. 'e' is an entity, not a
package. I don't think the tools are bending the rules in this case.
Charles Bailey
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