• VHDL2019 conditional compilation

    From ht lab@21:1/5 to All on Mon Feb 14 08:04:45 2022
    If you are a Modelsim/Questa user you might have spotted that 2022.1 has just been release and to my surprise it supports VHDL2019 conditional compilation!

    The documentation is a bit sketchy so here is how to use it:

    1) Define a VHDL2019 `if construct:

    `if CONST_OVERRIDE="1" then
    constant my_val: integer := 10;
    `else
    constant my_val: integer := 11;
    `end

    2) compile your code with:

    vcom test.vhd -vhpreprocess -definevh CONST_OVERRIDE=1

    3) run vsim

    you will notice that depending on the -definevh value you either get 10 or 11. Also note the use of double quotes in the code and no quotes on the vcom line.

    You will also have a bunch of predefined constants such as VHDL_VERSION, TOOL_VENDOR etc.

    Now fingers crossed they will add more VHDL2019 support.....

    Regards,
    Hans

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