Hello,

I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself.

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized.

Thanks

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On 15/12/2021 23:28, A wrote:

Hello,

I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself.

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized.

Thanks

in process (A, B, C).... there is no wait statement, so time didn't advances

HTH



--
Cet email a fait l'objet d'une analyse antivirus par AVG.
http://www.avg.com

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On Thursday, December 16, 2021 at 2:50:49 AM UTC-8, Maurice SAAB wrote:

On 15/12/2021 23:28, A wrote:

Hello,

I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself.

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized.

Thanks

in process (A, B, C).... there is no wait statement, so time didn't advances

HTH

--
Cet email a fait l'objet d'une analyse antivirus par AVG.
http://www.avg.com

Process is sensitive to A.B.C - so can't have wait statement in the process. No wait when there is sensitivity list - VHDL rule.

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On 16/12/2021 20:37, A wrote:

On Thursday, December 16, 2021 at 2:50:49 AM UTC-8, Maurice SAAB wrote:

On 15/12/2021 23:28, A wrote:

Hello,

I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself.

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized.

Thanks

in process (A, B, C).... there is no wait statement, so time didn't advances >>
HTH



--
Cet email a fait l'objet d'une analyse antivirus par AVG.
http://www.avg.com

Process is sensitive to A.B.C - so can't have wait statement in the process. No wait when there is sensitivity list - VHDL rule.

Seems working with my (old) simulator:
ENTER: At Time = 0 ns INPUT = 'U''U''U'
EXIT: At Time = 0 ns iOUT1 = 'U''U''U'
ENTER: At Time = 1 ns INPUT = '0''U''U'
EXIT: At Time = 1 ns iOUT1 = '0''U''U'
ENTER: At Time = 11 ns INPUT = '0''0''U'
EXIT: At Time = 11 ns iOUT1 = '0''0''U'
ENTER: At Time = 15 ns INPUT = '0''0''0'
EXIT: At Time = 15 ns iOUT1 = '0''0''0'
ENTER: At Time = 26 ns INPUT = '1''0''0'
EXIT: At Time = 26 ns iOUT1 = '1''0''0'
ENTER: At Time = 36 ns INPUT = '1''1''0'
EXIT: At Time = 36 ns iOUT1 = '1''1''0'
ENTER: At Time = 40 ns INPUT = '1''1''1'
EXIT: At Time = 40 ns iOUT1 = '1''1''1'

there is ENTER at 36ns when B changes

--- SoupGate-Win32 v1.05
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On 2021-12-15 15:28, A wrote:

Hello,

I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself.

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized.

Thanks

The main problem is that signals B and C are being driven by two
processes. Unless you are dealing with tri-state logic this is usually
a no-no. Remember that in VHDL a signal is not a variable in the sense
that you would think of a variable in a conventional programming
language. An assignment statement for a signal (<=) within a process or
in a stand-alone concurrent statement creates a driver for that signal.
So, in the example you pointed to, B and C have conflicting drivers.

Another problem is that signal B appears in the sensitivity list of the
first process and also appears on the left-hand side of an assignment
statement in that process. This is also usually a no-no since the
feedback can cause endless loops in some cases. (Trust me, over the
past few months I have been solving some simulator hang problems in
somebody else's logic caused by process feedback.)

Charles Bailey

--- SoupGate-Win32 v1.05
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On Thursday, December 16, 2021 at 11:38:15 AM UTC-8, Maurice SAAB wrote:

On 16/12/2021 20:37, A wrote:

On Thursday, December 16, 2021 at 2:50:49 AM UTC-8, Maurice SAAB wrote:

On 15/12/2021 23:28, A wrote:

Hello,

I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself.

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized.

Thanks

in process (A, B, C).... there is no wait statement, so time didn't advances

HTH



--
Cet email a fait l'objet d'une analyse antivirus par AVG.
http://www.avg.com

Process is sensitive to A.B.C - so can't have wait statement in the process. No wait when there is sensitivity list - VHDL rule.

Seems working with my (old) simulator:
ENTER: At Time = 0 ns INPUT = 'U''U''U'
EXIT: At Time = 0 ns iOUT1 = 'U''U''U'
ENTER: At Time = 1 ns INPUT = '0''U''U'
EXIT: At Time = 1 ns iOUT1 = '0''U''U'
ENTER: At Time = 11 ns INPUT = '0''0''U'
EXIT: At Time = 11 ns iOUT1 = '0''0''U'
ENTER: At Time = 15 ns INPUT = '0''0''0'
EXIT: At Time = 15 ns iOUT1 = '0''0''0'
ENTER: At Time = 26 ns INPUT = '1''0''0'
EXIT: At Time = 26 ns iOUT1 = '1''0''0'
ENTER: At Time = 36 ns INPUT = '1''1''0'
EXIT: At Time = 36 ns iOUT1 = '1''1''0'
ENTER: At Time = 40 ns INPUT = '1''1''1'
EXIT: At Time = 40 ns iOUT1 = '1''1''1'

there is ENTER at 36ns when B changes

Thanks Maurice. But the reason it worked for you is because I had changed the model (drive A first) to make it work. If you try it again, it'll show the behavior as I explained in my original post.

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On Thursday, December 16, 2021 at 5:10:05 PM UTC-8, Charles Bailey wrote:

On 2021-12-15 15:28, A wrote:

Hello,

I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself.

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized.

Thanks

The main problem is that signals B and C are being driven by two
processes. Unless you are dealing with tri-state logic this is usually
a no-no. Remember that in VHDL a signal is not a variable in the sense
that you would think of a variable in a conventional programming
language. An assignment statement for a signal (<=) within a process or
in a stand-alone concurrent statement creates a driver for that signal.
So, in the example you pointed to, B and C have conflicting drivers.

Another problem is that signal B appears in the sensitivity list of the first process and also appears on the left-hand side of an assignment statement in that process. This is also usually a no-no since the
feedback can cause endless loops in some cases. (Trust me, over the
past few months I have been solving some simulator hang problems in
somebody else's logic caused by process feedback.)

Charles Bailey

Thanks Charles. Multiple drivers is a good point. I was aware of this but I wanted to see if the process would at least enter once, when 'B' changes. I think since 'A' drives B and since A is 'U' at time zero; when B goes to '0', the multiple drivers get
resolved to 'U' and the sensitivity list does not see a change in 'B'. Confusing explanation but that's the only way I can see why the process does not trigger when 'B' changes at time 1ns. Thanks again.

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