On 12/05/2021 16:23, Dương Dương wrote:
i have flipflops.vhdl
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY flipflops IS
PORT (
clk : IN STD_LOGIC;
d : IN STD_LOGIC;
qa : OUT STD_LOGIC;
qb : OUT STD_LOGIC;
qc : OUT STD_LOGIC);
END ENTITY flipflops;
ARCHITECTURE beh OF flipflops IS
BEGIN -- ARCHITECTURE beh
ffa: PROCESS (clk, d) IS
BEGIN -- PROCESS ffa
IF clk = '1' THEN
qa <= d;
END IF;
END PROCESS ffa;
ffb: PROCESS (clk) IS
BEGIN -- PROCESS ffb
IF rising_edge(clk) THEN
qb <= d;
END IF;
END PROCESS ffb;
ffc: PROCESS (clk) IS
BEGIN -- PROCESS ffc
IF falling_edge(clk) THEN
qc <= d;
END IF;
END PROCESS ffc;
END ARCHITECTURE beh;
How can i complete flipflops_tb
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY flipflops_tb IS
END ENTITY flipflops_tb;
-------------------------------------------------------------------------------
ARCHITECTURE test OF flipflops_tb IS
-- component ports
SIGNAL clk : STD_LOGIC := '1';
SIGNAL d : STD_LOGIC;
SIGNAL qa : STD_LOGIC;
SIGNAL qb : STD_LOGIC;
SIGNAL qc : STD_LOGIC;
BEGIN -- ARCHITECTURE test
-- component instantiation
DUT : ENTITY work.flipflops
PORT MAP (
clk => clk,
d => d,
qa => qa,
qb => qb,
qc => qc);
-- clock generation
Clk <= NOT Clk AFTER 10 NS;
-- waveform generation
WaveGen_Proc : PROCESS
BEGIN
-- insert signal assignments here
d <= '0';
WAIT FOR 5 NS;
d <= '1';
WAIT FOR 3 NS;
END PROCESS WaveGen_Proc;
END ARCHITECTURE test;
-------------------------------------------------------------------------------
CONFIGURATION flipflops_tb_test_cfg OF flipflops_tb IS
FOR test
END FOR;
END flipflops_tb_test_cfg;
-------------------------------------------------------------------------------
thanks
Have you just posted your homework questions ?
MK
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