'Last_event is the time of the "last" event on a signal. In my simulation the signal has not had an event when it is first checked. The value returned seems to be a rather large value. I did some searching and didn't find this anywhere and don't have
a copy of the language reference manual.

Also, what is the definition of "last"? Is that the previous event or the current on if the signal has just had an event and no time has elapsed? I'm talking about a process with the signal as it's trigger. Will 'Last_event give the current time or
the previous time of change?

I'm trying to check setup and hold times. When they are 0, it can be a bit hard to distinguish.

--

Rick C.

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Did you ask Google?
Here is what Google says:
S'Last_event: the amount of time since last event occurred on S, if no event has yet occurred it returns Time'High

Here is what the VHDL LRM says:
S'LAST_EVENT
Kind: Function.
Prefix: Any signal denoted by the static signal name S.
Result type: Type TIME.
Result: The amount of time that has elapsed since the last event occurred on signal S. Specifically:
For a signal S, S'LAST_EVENT returns the smallest value T of type TIME such that
S'EVENT = TRUE during any simulation cycle at time NOW – T, if such a value exists;
otherwise, it returns TIME'HIGH.

Hence if 'event is true, then 'last_event = 0.

You might want to look at the Vital timing library as it has setup and hold checkers. If you cannot find anything else, I recommend Rick Munden's book, "ASIC and FPGA Verification"

If you truely want to write your own, you might want to read up on 'delayed and postponed. Although, I prefer to log process run times to instead and use the function now.

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On Tuesday, November 10, 2020 at 8:58:57 PM UTC-5, Jim Lewis wrote:

Did you ask Google?
Here is what Google says:
S'Last_event: the amount of time since last event occurred on S, if no event has yet occurred it returns Time'High

Here is what the VHDL LRM says:
S'LAST_EVENT
Kind: Function.
Prefix: Any signal denoted by the static signal name S.
Result type: Type TIME.
Result: The amount of time that has elapsed since the last event occurred on signal S. Specifically:
For a signal S, S'LAST_EVENT returns the smallest value T of type TIME such that
S'EVENT = TRUE during any simulation cycle at time NOW – T, if such a value exists;
otherwise, it returns TIME'HIGH.

Hence if 'event is true, then 'last_event = 0.

You might want to look at the Vital timing library as it has setup and hold checkers. If you cannot find anything else, I recommend Rick Munden's book, "ASIC and FPGA Verification"

If you truely want to write your own, you might want to read up on 'delayed and postponed. Although, I prefer to log process run times to instead and use the function now.

Where did you find that on Google? I didn't find anything useful. I did post this to stackexchange.com and got a response a couple of days ago. As you say, the standard says assigned signals are time'high which makes them easy to detect.

Thanks for the suggestions. I'm about done with this test bench, but I'll keep Vital in mind for the next one.

When it came to the definition of "last" it reminded me of the Seinfeld joke about the meaning of "next" Wednesday. "If I had meant THIS Wednesday, I've have said THIS Wednesday".

--

Rick C.

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