I can't figure out what is wrong with this left side aggregate. The right side is clearly defined. The left side is a std_logic combined with an unsigned which is not inappropriate as far as I can tell. Synplify and ActiveHDL both compile it ok, but
ActiveHDL gives a run time error...

# RUNTIME: Fatal Error: RUNTIME_0046 VHDL_test.vhd (27): Incompatible ranges; left: (0 to 3), right: (0 downto 0).

signal count, nxt_cnt : unsigned(2 downto 0) := (others => '0');
signal Test_Out_v : std_logic := '0';
begin
Clk_gen: Clk <= not Clk after Clock_Half_Period;

(Carry_Out, nxt_cnt) <= RESIZE(count, nxt_cnt'length + 1) - 1;

Pointing to the above line. It doesn't point to any part of the line.

I'm stumped on this one.

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Rick C.

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On Saturday, October 17, 2020 at 12:16:22 AM UTC-4, gnuarm.del...@gmail.com wrote:

I can't figure out what is wrong with this left side aggregate. The right side is clearly defined. The left side is a std_logic combined with an unsigned which is not inappropriate as far as I can tell. Synplify and ActiveHDL both compile it ok, but

ActiveHDL gives a run time error...

# RUNTIME: Fatal Error: RUNTIME_0046 VHDL_test.vhd (27): Incompatible ranges; left: (0 to 3), right: (0 downto 0).

<snip>

I'm stumped on this one.

Try using Modelsim (it works using the code you posted in comp.arch.fpga along with the change you noted in this post) or GHDL (I didn't try it).

Kevin Jennings

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On Tuesday, October 20, 2020 at 9:19:34 AM UTC-4, KJ wrote:

On Saturday, October 17, 2020 at 12:16:22 AM UTC-4, gnuarm.del...@gmail.com wrote:

I can't figure out what is wrong with this left side aggregate. The right side is clearly defined. The left side is a std_logic combined with an unsigned which is not inappropriate as far as I can tell. Synplify and ActiveHDL both compile it ok, but

ActiveHDL gives a run time error...

# RUNTIME: Fatal Error: RUNTIME_0046 VHDL_test.vhd (27): Incompatible ranges; left: (0 to 3), right: (0 downto 0).

<snip>

I'm stumped on this one.

Try using Modelsim (it works using the code you posted in comp.arch.fpga along with the change you noted in this post) or GHDL (I didn't try it).

Changing literally any part of this assignment allows it to work. Obviously getting rid of the left side aggregate allows it work. Changing the RESIZE to a simple concatenation allows it to work ("0" & count). Changing the integer 1 to an unsigned
constant (in spite of the name) allows it to work. I have no doubt it is an Active-HDL bug at this point.

Now my problem is how to let Aldec know the bug exists. Neither Aldec nor Lattice has a mechanism to report bugs if you aren't currently under a maintenance plan. Lattice doesn't even have forums any longer. They used to have people scan the forums
once in a while. Dropping the forums cuts off all means of unpaid support. I haven't found anything at Aldec either.

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Rick C.

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Can you post a minimum example that can be pasted into a file and independently tested?

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On Thursday, October 22, 2020 at 4:08:51 PM UTC-4, Jim Lewis wrote:

Can you post a minimum example that can be pasted into a file and independently tested?

Sure, this has been hashed out in stackexchange to the point I'm pretty convinced it is a simulator bug. It works on Modelsim and ghdl or if very minor changes are made to the code as noted in the comments.

I use 4 space tabs. Google shouldn't wrap the lines but your reader might.

It will be interesting to find that it is my code and not a bug.


-- Test synthesis of counters and carry out flags
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- use work.Common.all;

entity VHDL_test is
generic(
CLK_HZ : REAL := 33.554432E6 );
port(
-- Clk : in std_logic := '1';
Cnt_En : in std_logic := '1';
Test_Out_a : out std_logic;
Carry_Out_a : out std_logic
);
end VHDL_test;

architecture TB_ARCH of VHDL_test is
constant Clock_Half_Period : time := 500 ms / CLK_HZ; -- 14901 ps;
constant Cntr_Width : positive := 8;
constant Cntr_Modulus : positive := 2**Cntr_Width;
constant One_uns : unsigned(Cntr_Width downto 0) := "000000001";
signal Clk : std_logic := '1';
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => '0');
begin

Clk_gen: Clk <= not Clk after Clock_Half_Period; -- comment out for synth

(Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a'length + 1) - 1; -- fails
-- (Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a'length + 1) - One_uns; -- works
-- (Carry_Out_a, nxt_cnt_a) <= ("0" & Count_a) - 1; -- works

test_ag: process (Clk) is
begin
if rising_edge(Clk) then
Test_Out_a <= Carry_Out_a;
if (Cnt_En OR not Carry_Out_a) then
Count_a <= nxt_cnt_a;
end if;
end if;
end process test_ag;

end TB_ARCH; -- VHDL_test


--

Rick C.

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