when i try to compile thisin ModelSim..

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

LIBRARY work;

ENTITY Lab_2 IS
PORT
(
ina1 : IN STD_LOGIC;
ina2 : IN STD_LOGIC;
ina3 : IN STD_LOGIC;
ina4 : IN STD_LOGIC;
inb1 : IN STD_LOGIC;
inb2 : IN STD_LOGIC;
inb3 : IN STD_LOGIC;
inb4 : IN STD_LOGIC;
o1 : OUT STD_LOGIC;
o2 : OUT STD_LOGIC;
o3 : OUT STD_LOGIC;
o4 : OUT STD_LOGIC;
outacarreo : OUT STD_LOGIC
);
END Lab_2;

ARCHITECTURE bdf_type OF Lab_2 IS

--ATTRIBUTE black_box : BOOLEAN;
--ATTRIBUTE noopt : BOOLEAN;

COMPONENT 7483
PORT(C0 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
S3 : OUT STD_LOGIC;
S4 : OUT STD_LOGIC;
S2 : OUT STD_LOGIC;
C4 : OUT STD_LOGIC;
S1 : OUT STD_LOGIC)
END COMPONENT;
--ATTRIBUTE black_box OF 7483 : COMPONENT IS true;
--ATTRIBUTE noopt OF 7483 : COMPONENT IS true;

SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL o11 : STD_LOGIC;
SIGNAL o12 : STD_LOGIC;
SIGNAL o13 : STD_LOGIC;
SIGNAL o14 : STD_LOGIC;

BEGIN
SYNTHESIZED_WIRE_16 <= '0';



b2v_inst : 7483
PORT MAP(B4 => inb4,
A1 => ina1,
A2 => ina2,
B1 => inb1,
B2 => inb2,
A3 => ina3,
B3 => inb3,
A4 => ina4,
S3 => SYNTHESIZED_WIRE_19,
S4 => SYNTHESIZED_WIRE_20,
S2 => SYNTHESIZED_WIRE_17,
C4 => SYNTHESIZED_WIRE_12,
S1 => SYNTHESIZED_WIRE_1);


b2v_inst1 : 7483
PORT MAP(B4 => SYNTHESIZED_WIRE_16,
A1 => SYNTHESIZED_WIRE_1,
A2 => SYNTHESIZED_WIRE_17,
B1 => SYNTHESIZED_WIRE_16,
B2 => SYNTHESIZED_WIRE_18,
A3 => SYNTHESIZED_WIRE_19,
B3 => SYNTHESIZED_WIRE_18,
A4 => SYNTHESIZED_WIRE_20,
S3 => o13,
S4 => o14,
S2 => o12,
C4 => SYNTHESIZED_WIRE_15,
S1 => o11);


SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_20;


SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_19 OR SYNTHESIZED_WIRE_17;


SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13;


outacarreo <= SYNTHESIZED_WIRE_18 OR SYNTHESIZED_WIRE_15;

o1 <= o11;
o2 <= o12;
o3 <= o13;
o4 <= o14;

END bdf_type;

it gives me this error...

** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER

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On Monday, September 21, 2020 at 8:31:40 PM UTC-4, Victor Salazar wrote:

when i try to compile thisin ModelSim..

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

LIBRARY work;

ENTITY Lab_2 IS
PORT
(
ina1 : IN STD_LOGIC;
ina2 : IN STD_LOGIC;
ina3 : IN STD_LOGIC;
ina4 : IN STD_LOGIC;
inb1 : IN STD_LOGIC;
inb2 : IN STD_LOGIC;
inb3 : IN STD_LOGIC;
inb4 : IN STD_LOGIC;
o1 : OUT STD_LOGIC;
o2 : OUT STD_LOGIC;
o3 : OUT STD_LOGIC;
o4 : OUT STD_LOGIC;
outacarreo : OUT STD_LOGIC
);
END Lab_2;

ARCHITECTURE bdf_type OF Lab_2 IS

--ATTRIBUTE black_box : BOOLEAN;
--ATTRIBUTE noopt : BOOLEAN;

COMPONENT 7483
PORT(C0 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
S3 : OUT STD_LOGIC;
S4 : OUT STD_LOGIC;
S2 : OUT STD_LOGIC;
C4 : OUT STD_LOGIC;
S1 : OUT STD_LOGIC)
END COMPONENT;
--ATTRIBUTE black_box OF 7483 : COMPONENT IS true;
--ATTRIBUTE noopt OF 7483 : COMPONENT IS true;

SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL o11 : STD_LOGIC;
SIGNAL o12 : STD_LOGIC;
SIGNAL o13 : STD_LOGIC;
SIGNAL o14 : STD_LOGIC;

BEGIN
SYNTHESIZED_WIRE_16 <= '0';

b2v_inst : 7483
PORT MAP(B4 => inb4,
A1 => ina1,
A2 => ina2,
B1 => inb1,
B2 => inb2,
A3 => ina3,
B3 => inb3,
A4 => ina4,
S3 => SYNTHESIZED_WIRE_19,
S4 => SYNTHESIZED_WIRE_20,
S2 => SYNTHESIZED_WIRE_17,
C4 => SYNTHESIZED_WIRE_12,
S1 => SYNTHESIZED_WIRE_1);

b2v_inst1 : 7483
PORT MAP(B4 => SYNTHESIZED_WIRE_16,
A1 => SYNTHESIZED_WIRE_1,
A2 => SYNTHESIZED_WIRE_17,
B1 => SYNTHESIZED_WIRE_16,
B2 => SYNTHESIZED_WIRE_18,
A3 => SYNTHESIZED_WIRE_19,
B3 => SYNTHESIZED_WIRE_18,
A4 => SYNTHESIZED_WIRE_20,
S3 => o13,
S4 => o14,
S2 => o12,
C4 => SYNTHESIZED_WIRE_15,
S1 => o11);

SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_20;

SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_19 OR SYNTHESIZED_WIRE_17;

SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13;

outacarreo <= SYNTHESIZED_WIRE_18 OR SYNTHESIZED_WIRE_15;

o1 <= o11;
o2 <= o12;
o3 <= o13;
o4 <= o14;

END bdf_type;

it gives me this error...

** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER

The line above is saying there is an error detected at line 50. Do you know where line 50 is?

The other clue they give is when they say "near 7483". Where do you see 7483 and how is it being used?

The final clue is the words, "expecting IDENTIFIER". If they are referring to "7483" and saying "expecting IDENTIFIER" what does that tell you?

How much VHDL have you written? Do you know the rules for identifiers in VHDL? Check your references.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

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Victor Salazar <viquinhoslmetal2.014@gmail.com> writes:

it gives me this error...

** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER

In VHDL basic identifiers start with a letter. In other words, you can't
name your component 7483, that's a syntax error. (There are extended identifiers too but those don't allow 7483 as an identifier either.)

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 22, 2020 at 3:55:27 PM UTC-4, Anssi Saari wrote:

Victor Salazar <viquinhosl...@gmail.com> writes:

it gives me this error...

** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER

In VHDL basic identifiers start with a letter. In other words, you can't
name your component 7483, that's a syntax error. (There are extended identifiers too but those don't allow 7483 as an identifier either.)

If you want 7483 as an identifier, you need to add the extended identifier backslash character before and after

These are wrong...
COMPONENT 7483
b2v_inst1 : 7483

These are correct
COMPONENT \7483\
b2v_inst1 : \7483\

Kevin Jennings

--- SoupGate-Win32 v1.05
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On 22/09/2020 21:29, KJ wrote:

On Tuesday, September 22, 2020 at 3:55:27 PM UTC-4, Anssi Saari wrote:

Victor Salazar <viquinhosl...@gmail.com> writes:

it gives me this error...

** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER

In VHDL basic identifiers start with a letter. In other words, you can't
name your component 7483, that's a syntax error. (There are extended
identifiers too but those don't allow 7483 as an identifier either.)

If you want 7483 as an identifier, you need to add the extended identifier backslash character before and after

These are wrong...
COMPONENT 7483
b2v_inst1 : 7483

These are correct
COMPONENT \7483\
b2v_inst1 : \7483\

Kevin Jennings

Interesting, I have never seen this in any source code, I just tried it
out and indeed it works fine. I suspect this is just a side effect on
the language and not something VHDL users have actually asked for?

Thanks,
Hans.
www.ht-lab.com

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HT-Lab <hans64@htminuslab.com> writes:

On 22/09/2020 21:29, KJ wrote:

These are correct
COMPONENT \7483\
b2v_inst1 : \7483\

Kevin Jennings

Interesting, I have never seen this in any source code, I just tried
it out and indeed it works fine. I suspect this is just a side effect
on the language and not something VHDL users have actually asked for?

It was apparently added to VHDL'93 so I guess someone did ask for it. I
think it's common in synthesis generated names at least? Anyways, I
think the syntax is awful and didn't show an example for that reason.

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On Wednesday, September 23, 2020 at 6:46:10 AM UTC-4, Anssi Saari wrote:

HT-Lab <han...@htminuslab.com> writes:

On 22/09/2020 21:29, KJ wrote:

These are correct
COMPONENT \7483\
b2v_inst1 : \7483\

Kevin Jennings

Interesting, I have never seen this in any source code, I just tried
it out and indeed it works fine. I suspect this is just a side effect
on the language and not something VHDL users have actually asked for?

It was apparently added to VHDL'93 so I guess someone did ask for it. I think it's common in synthesis generated names at least? Anyways, I
think the syntax is awful and didn't show an example for that reason.

I use the extended identifier backslash in simulation models for ICs as a way for the VHDL names to remain faithful to the datasheet. In the original post, the '7483' is clearly referring to an IC. But an actual datasheet that you could (and should)
reference in your model might be the SN7483 . So to avoid the extended character backslash, I would call the entity SN7483 and there is no confusion.

Where it gets trickier can be for the signal pin names on the IC. Names like the following come up on old and new parts:
1A
io2/lvds15p/crc_error

In the first case you could rename it as 'A1', in the second maybe you replace the forward slash with an underscore but these changes morph the VHDL model pin name away from what the manufacturer has named the pin so it can lead to confusion by any
future user of that model. It's 'better' to just use the manufacturer's pin name in the form of an extended identifier like this

\1A\
\io2/lvds15p/crc_error\

'Better' of course is a relative thing that depends on the user. Because the extended identifier notation is not commonly known, it can create its own confusion. However, renaming things creates confusion as well. I don't know for sure what motivated
the change to the language in 1993 that added the extended identifier but I suspect that it was for exactly this situation of being able to specify the manufacturer's name 'as-is'.

For one's own design code, the designer names the entity and the in/out signals so there is probably no good reason for using the extended identifier.

Kevin Jennings

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