On Thursday, September 17, 2020 at 8:35:17 PM UTC-4, gnuarm.del...@gmail.com wrote:work with any size vectors, those vectors still must have defined ranges. Otherwise, how can it check that the vectors are the same size?
Sound_Run <= Alarm_Src ?/= (others => '0');
The compiler complains that it doesn't understand what size the aggregate should be. Is that because while Alarm_Src is well defined, the comparison operator can accept many different operand widths and the tool can't see across the operator???
Basically, yes. However, if all somebody told you is "(others => '0')", and asked how wide the vector is, you wouldn't be able to answer the question. The compiler is the same way. It needs to know the width of the vector. While the operator can
Kevin Jennings
Sound_Run <= Alarm_Src ?/= (others => '0');
The compiler complains that it doesn't understand what size the aggregate should be. Is that because while Alarm_Src is well defined, the comparison operator can accept many different operand widths and the tool can't see across the operator???
On Friday, September 18, 2020 at 12:51:23 PM UTC-4, KJ wrote:work with any size vectors, those vectors still must have defined ranges. Otherwise, how can it check that the vectors are the same size?
On Thursday, September 17, 2020 at 8:35:17 PM UTC-4, gnuarm.del...@gmail.com wrote:
Basically, yes. However, if all somebody told you is "(others => '0')", and asked how wide the vector is, you wouldn't be able to answer the question. The compiler is the same way. It needs to know the width of the vector. While the operator can
Sound_Run <= Alarm_Src ?/= (others => '0');
The compiler complains that it doesn't understand what size the aggregate should be. Is that because while Alarm_Src is well defined, the comparison operator can accept many different operand widths and the tool can't see across the operator???
an intent that is patently obvious which was eventually fixed in the language like "000" being assigned to a std_logic_vector because the tools didn't know you weren't trying to assign a bit vector to an slv.
Kevin Jennings
The vector is as wide as the other input to the ?/= operator. I would expect that to be obvious to anyone looking at the code. But it's not obvious to the tool. That's my point. Many times in the past I recall the tool not being able to under stand
This would seem to be another case of the tools not being able to understand what is actually rather obvious. I keep saying I'm going to learn Verilog. Maybe I should have used this project as my learning curve.
On 18/09/2020 18:01, Rick C wrote:work with any size vectors, those vectors still must have defined ranges. Otherwise, how can it check that the vectors are the same size?
On Friday, September 18, 2020 at 12:51:23 PM UTC-4, KJ wrote:
On Thursday, September 17, 2020 at 8:35:17 PM UTC-4, gnuarm.del...@gmail.com wrote:
Basically, yes. However, if all somebody told you is "(others => '0')", and asked how wide the vector is, you wouldn't be able to answer the question. The compiler is the same way. It needs to know the width of the vector. While the operator can
Sound_Run <= Alarm_Src ?/= (others => '0');
The compiler complains that it doesn't understand what size the aggregate should be. Is that because while Alarm_Src is well defined, the comparison operator can accept many different operand widths and the tool can't see across the operator???
stand an intent that is patently obvious which was eventually fixed in the language like "000" being assigned to a std_logic_vector because the tools didn't know you weren't trying to assign a bit vector to an slv.
Kevin Jennings
The vector is as wide as the other input to the ?/= operator. I would expect that to be obvious to anyone looking at the code. But it's not obvious to the tool. That's my point. Many times in the past I recall the tool not being able to under
This would seem to be another case of the tools not being able to understand what is actually rather obvious. I keep saying I'm going to learn Verilog. Maybe I should have used this project as my learning curve.
I'm not so sure that Verilog will help you much, with VHDL the compiler refuses to guess, sometimes pedantically. Verilog is like an
enthusiastic puppy, it tries to guess what you want and sometimes gets
it horribly wrong, and you don't find out until it doesn't work.
This would seem to be another case of the tools not being able to understand what is actually rather obvious. I keep saying I'm going to learn Verilog. Maybe I shouldhave used this project as my learning curve.
I'm not so sure that Verilog will help you much, with VHDL the compiler >refuses to guess, sometimes pedantically. Verilog is like an
enthusiastic puppy, it tries to guess what you want and sometimes gets
it horribly wrong, and you don't find out until it doesn't work.
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