On 19/09/2019 15:01, Rick C wrote:
On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote:
On 07/09/2019 13:38, the.yasep@gmail.com wrote:
WOOOooooops ! Hans reported it yesterday :-DNo problem, the more people report it the better.
I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is
OK as it looks like VHDL2019 brings the 2 languages closer together
(similar to what Accellera did with PSL and SVA).
VHDL2019 will have DPI, interfaces and a preprocessor using the same
unreadable "`" character as SV does :-(
Hans
www.ht-lab.com
I don't know what that character is. It doesn't seem to be the single quote
"'". I guess it is "`"... Does that have a name? Google seems to search on
it ok. It's called a "grave accent" and has uses in programing, also called
"backquote" or "backtick".
Yes, I know it from Verilog as the backtick but officially it is called a grave
accent (also in the VHDL2019 LRM). I guess the steering group chose that character as it was already used for VHDL encryption and Verilog directives. Also with modern editors you quickly see if you are using the wrong character but still as an old C/ASM programmer I would have preferred '#'.
I guess I vaguely recall seeing it on keyboards, but I don't recall ever using
it for anything in my 45 year career, the only key on the keyboard like that I
think... well, other than SYSRQ I guess. I've at least played with SYSRQ to
see what it does... nothing that I've ever found.
I vaguely remember you posting that you prefer Verilog over VHDL so you must have used it many times? Perhaps like me your memory is not that great any more.
Regards,
Hans
www.ht-lab.com
On 19/09/2019 15:01, Rick C wrote:backtick".
On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote:
On 07/09/2019 13:38, the.yasep@gmail.com wrote:
WOOOooooops ! Hans reported it yesterday :-DNo problem, the more people report it the better.
I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is
OK as it looks like VHDL2019 brings the 2 languages closer together
(similar to what Accellera did with PSL and SVA).
VHDL2019 will have DPI, interfaces and a preprocessor using the same
unreadable "`" character as SV does :-(
Hans
www.ht-lab.com
I don't know what that character is. It doesn't seem to be the single quote "'". I guess it is "`"... Does that have a name? Google seems to search on it ok. It's called a "grave accent" and has uses in programing, also called "backquote" or "
Yes, I know it from Verilog as the backtick but officially it is called
a grave accent (also in the VHDL2019 LRM). I guess the steering group
chose that character as it was already used for VHDL encryption and
Verilog directives. Also with modern editors you quickly see if you are using the wrong character but still as an old C/ASM programmer I would
have preferred '#'.
does... nothing that I've ever found.I guess I vaguely recall seeing it on keyboards, but I don't recall ever using it for anything in my 45 year career, the only key on the keyboard like that I think... well, other than SYSRQ I guess. I've at least played with SYSRQ to see what it
I vaguely remember you posting that you prefer Verilog over VHDL so you
must have used it many times? Perhaps like me your memory is not that
great any more.
Jim Lewis shared the news :
IEEE Std 1076-2019 has been approved by the IEEE SASB today.
What a ride it was !
I'm still frustrated by the crazy process and the refusal of my own tiny feature request but it's good to see that venerable language still moving forward and kicking Verilog's ass ;-)
yg
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