• About Memory Ordering and Atomicity..

    From Wisdom90@21:1/5 to All on Thu Jan 16 14:46:07 2020

    About Memory Ordering and Atomicity..

    Read the following it says:

    "The performance gain from allowing memory reordering is small, and it
    doesn't make up for the extra headaches that come from difficult-to-find failures."

    Read more here:


    So then i think what i wrote previously about it is true, read i again carefully:

    Here is another problem with ARM processors..

    About SC and TSO and RMO hardware memory models..

    I have just read the following webpage about the performance difference between: SC and TSO and RMO hardware memory models

    I think TSO is better, it is just around 3% ~ 6% less performance
    than RMO and it is a simpler programming model than RMO. So i think ARM
    must support TSO to be compatible with x86 that is TSO.

    Read more here to notice it:


    About memory models and sequential consistency:

    As you have noticed i am working with x86 architecture..

    Even though x86 gives up on sequential consistency, it’s among the most well-behaved architectures in terms of the crazy behaviors it allows.
    Most other architectures implement even weaker memory models.

    ARM memory model is notoriously underspecified, but is essentially a
    form of weak ordering, which provides very few guarantees. Weak ordering
    allows almost any operation to be reordered, which enables a variety of hardware optimizations but is also a nightmare to program at the lowest

    Read more here:


    Memory Models: x86 is TSO, TSO is Good

    Essentially, the conclusion is that x86 in practice implements the old
    SPARC TSO memory model.

    The big take-away from the talk for me is that it confirms the
    observation made may times before that SPARC TSO seems to be the optimal
    memory model. It is sufficiently understandable that programmers can
    write correct code without having barriers everywhere. It is
    sufficiently weak that you can build fast hardware implementation that
    can scale to big machines.

    Read more here:


    Thank you,
    Amine Moulay Ramdane.

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