I am new to compilers so maybe what I am about to describe is normal behaviour. My current retargeting efforts are starting to generate working code. However, it has a lot of the instruction sequence below in there:
#1 stw r1,-2(bp)
#2 ldw r4, -2(bp)
#3 addi r4,1,r4
#4 stw r4,-2(bp)
#5 ldw r1, -2(bp)
We are storing something in memory from register-1 (R1). Then reloading that value in R4. Do something with it. Store it in memory. Then immediately reloading that again.
It's obvious instructions #2 and #5 could be avoided with better register selection. Is this something i can tweak in my .md file somehow? Or is this just normal compiler behaviour?
Thanks,
Erwin
I fully agree of course.
I was just wondering if there was something obvious I was missing in the lcc machine description language.
What I gather is that any optimisation for these types of occurrences will be separate from lcc.
Thx,
Erwin
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