On Monday, June 23, 2014 at 3:35:52 AM UTC-5, Russell Dill wrote:
As part of my research, I needed a BCH encoder/decoder engine. Sadly, such a thing has no existed under a permissive license. Even more depressing is that many students seem to submit Verilog or VHDL engines as a project (or even research), but never
release anything that is usable.
Anyway, I'm releasing a BSD licensed Verilog BCH encoder/decoder. It offers:
* Parallel input/output
* Modular components that can be shared across multiple decoders
* Automatic selection of BCH parameters based on data size and errors to be corrected
* Specialized error locators for 1 error and 2 error codes
* Parallel or serial error polynomial generator for codes with 2 or more errors
https://github.com/russdill/bch_verilog
I'm releasing this under BSD because I'd like to see the code used as widely as possible, but I'd still like to get feedback and hopefully improvements merged back in.
As an example, a decoder for a 512 byte data block that corrects up to 12 errors with an 8 bit wide input and an 8 bit wide output currently occupies 1635 slices and operates at up to 191 MHz on a Virtex-6 LX240T-3. Such a decoder would take input for
532 clock cycles (512 data bytes, 20 ecc bytes), calculate for about 28 clock cycles, and then produce output for 512 clock cycles.
The code currently compiles on Icarus Verilog (latest git) and Xilinx XST/Isim (tested with 14.5).
Hi Russell, Are you interested in a small project around FPGA: if yes, is it possible to have a phone or email conversation with you?
Thanks,
Tariq
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