My SSE-FPU generates the following NaNs:
* When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD
and one of both operands is a NaN, the result has the sign of the NaN
-operand and the lower 51 bits of the mantissa of the result is loa-
ded with the lower 51 bits of the mantissa of the NaN-operand.
My SSE-FPU generates the following NaNs:
* When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD
and one of both operands is a NaN, the result has the sign of the NaN
-operand and the lower 51 bits of the mantissa of the result is loa-
ded with the lower 51 bits of the mantissa of the NaN-operand.
* When both operations are NaN, the result is loaded with the sign of
the destination-register and the lower 51 bits of the result-mantissa
is loaded with the lower 51 bits of the destination-register before
the operation. So the associative law doesn't count here and the order
of the operands in a multiplication does count!
* When I do a SQRTSD on a NaN-value, the result has the sign of the
NaN-operand and the lower 51 bits of the result is loaded with the
lower 51 bits of the operand.
* When I do a multiplication of infinity with zero or infinity, I always
get -NaN as a result (binary representation 0xFFF8000000000000u).
Is this behaviour determined anywhere in the IEEE-754-standard?
In particular operations on NaN(s) intentionally breaks associativity,
look at comparisons.
Am 19.06.2016 um 00:08 schrieb Terje Mathisen:
In particular operations on NaN(s) intentionally breaks associativity,
look at comparisons.
I found a funny thing: When operating on two NaNs with the x87-FPU,
the lower 51 bits of the result is loaded with the larger value of
the lower 51 bits of both operands.
Bonita Montero wrote:
Am 19.06.2016 um 00:08 schrieb Terje Mathisen:
In particular operations on NaN(s) intentionally breaks associativity,
look at comparisons.
I found a funny thing: When operating on two NaNs with the x87-FPU,
the lower 51 bits of the result is loaded with the larger value of
the lower 51 bits of both operands.
Not funny:
This is a very natural result of having an internal pathway that sorts
the inputs into larger/smaller (ignoring sign), which is something you
need if you are going to subtract.
It doesn't matter for FMUL or FADD, except when an FADD has inputs with opposite signs and really was a FSUB.
For FDIV however you need to skip that compare/swap network, but FDIV is
an order of magnitude slower anyway.
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